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參數(shù)資料
| 型號(hào)： | XA3S1200E-4FTG256I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 7/37頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA SPARTAN3E 1200K 256FTBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-3E XA |
| LAB/CLB數(shù)： | 8672 |
| 邏輯元件/單元數(shù)： | 19512 |
| RAM 位總計(jì)： | 516096 |
| 輸入/輸出數(shù)： | 190 |
| 門(mén)數(shù)： | 1200000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
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DS635 (v2.0) September 9, 2009
Product Specification
15
R
Table 14: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Symbol
Description
Conditions
IFD_
DELAY_
VALUE=
Device
-4 Speed
Grade
Units
Min
Setup Times
TPSDCM
When writing to the Input Flip-Flop
(IFF), the time from the setup of
data at the Input pin to the active
transition at a Global Clock pin.
The DCM is used. No Input Delay
is programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 0,
with DCM(4)
0
XA3S100E
2.98
ns
XA3S250E
2.59
ns
XA3S500E
2.59
ns
XA3S1200E
2.58
ns
XA3S1600E
2.59
ns
TPSFD
When writing to IFF, the time from
the setup of data at the Input pin to
an active transition at the Global
Clock pin. The DCM is not used.
The Input Delay is programmed.
LVCMOS25(2),
IFD_DELAY_VALUE =
default software setting
2
XA3S100E
3.58
ns
3
XA3S250E
3.91
ns
2
XA3S500E
4.02
ns
5
XA3S1200E
5.52
ns
4
XA3S1600E
4.46
ns
Hold Times
TPHDCM
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is used. No Input Delay is
programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 0,
with DCM(4)
0
XA3S100E
–0.52
ns
XA3S250E
0.14
ns
XA3S500E
0.14
ns
XA3S1200E
0.15
ns
XA3S1600E
0.14
ns
TPHFD
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is not used. The Input Delay
is programmed.
LVCMOS25(3),
IFD_DELAY_VALUE =
default software setting
2
XA3S100E
–0.24
ns
3
XA3S250E
–0.32
ns
2
XA3S500E
–0.49
ns
5
XA3S1200E
–0.63
ns
4
XA3S1600E
–0.39
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in
2.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 17. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 17. If this is true of the data Input, subtract
the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s
active edge.
4.
DCM output jitter is included in all measurements.
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