參數(shù)資料
型號： XA3S1200E-4FTG256I
廠商： Xilinx Inc
文件頁數(shù)： 20/37頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN3E 1200K 256FTBGA
標準包裝： 90
系列： Spartan®-3E XA
LAB/CLB數(shù)： 8672
邏輯元件/單元數(shù)： 19512
RAM 位總計： 516096
輸入/輸出數(shù)： 190
門數(shù)： 1200000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-LBGA
供應商設備封裝： 256-FTBGA
DS635 (v2.0) September 9, 2009
Product Specification
27
R
Phase Shifter
Table 29: Switching Characteristics for the DFS
Symbol
Description
Device
-4 Speed Grade
Units
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_FX
Frequency for the CLKFX and CLKFX180 outputs
All
5
311
MHz
Output Clock Jitter(2,3)
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and CLKFX180
outputs
All
Typ
Max
CLKIN <20 MHz
See Note 4
ps
CLKIN > 20 MHz
±[1% of
CLKFX
period
+ 100]
±[1% of
CLKFX
period
+ 200]
ps
Duty Cycle(5,6)
CLKOUT_DUTY_CYCLE_FX
Duty cycle precision for the CLKFX and CLKFX180 outputs,
including the BUFGMUX and clock tree duty-cycle distortion
All
-±[1% of
CLKFX
period
+ 400]
ps
Phase Alignment(6)
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX output and the DLL CLK0
output when both the DFS and DLL are used
All
-
±200
ps
CLKOUT_PHASE_FX180
Phase offset between the DFS CLKFX180 output and the DLL
CLK0 output when both the DFS and DLL are used
All
-±[1% of
CLKFX
period
+ 300]
ps
Lock Time
LOCK_FX(2)
The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. The DFS asserts LOCKED
when the CLKFX and CLKFX180 signals
are valid. If using both the DLL and the DFS,
use the longer locking time.
5 MHz < FCLKIN <
15 MHz
All
-5
ms
FCLKIN > 15 MHz
-450
μs
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 6 and Table 28.
2.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
3.
Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching). Output
jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching
frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.
4.
Use the Spartan-3A Jitter Calculator (www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip) to estimate DFS output jitter. Use the
Clocking Wizard to determine jitter for a specific design.
5.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
6.
Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies a maximum jitter
of “±[1% of CLKFX period + 300]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 300 ps] = ±400 ps.
Table 30: Recommended Operating Conditions for the PS in Variable Phase Mode
Symbol
Description
-4 Speed Grade
Units
Min
Max
Operating Frequency Ranges
PSCLK_FREQ
(FPSCLK)
Frequency for the PSCLK input
1
167
MHz
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK period
40%
60%
-
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