參數(shù)資料
型號: XA3S1200E-4FTG256I
廠商: Xilinx Inc
文件頁數(shù): 29/37頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN3E 1200K 256FTBGA
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-3E XA
LAB/CLB數(shù): 8672
邏輯元件/單元數(shù): 19512
RAM 位總計: 516096
輸入/輸出數(shù): 190
門數(shù): 1200000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
DS635 (v2.0) September 9, 2009
Product Specification
35
R
IEEE 1149.1/1553 JTAG Test Access Port Timing
Table 44: Timing for the JTAG Test Access Port
Symbol
Description
-4 Speed Grade
Units
Min
Max
Clock-to-Output Times
TTCKTDO
The time from the falling transition on the TCK pin
to data appearing at the TDO pin
1.0
11.0
ns
Setup Times
TTDITCK
The time from the setup of data at the TDI pin to
the rising transition at the TCK pin
7.0
-ns
TTMSTCK
The time from the setup of a logic level at the TMS
pin to the rising transition at the TCK pin
7.0
-ns
Hold Times
TTCKTDI
The time from the rising transition at the TCK pin
to the point when data is last held at the TDI pin
0
-ns
TTCKTMS
The time from the rising transition at the TCK pin
to the point when a logic level is last held at the
TMS pin
0
-ns
Clock Timing
TCCH
The High pulse width at the TCK pin
5
-ns
TCCL
The Low pulse width at the TCK pin
5
-ns
FTCK
Frequency of the TCK signal
-25
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 6.
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