參數(shù)資料
型號: XA3S700A-4FGG400I
廠商: Xilinx Inc
文件頁數(shù): 41/57頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3A 700K 400-FBGA
產(chǎn)品培訓(xùn)模塊: Extended Spartan 3A FPGA Family
標準包裝: 60
系列: Spartan®-3A XA
LAB/CLB數(shù): 1472
邏輯元件/單元數(shù): 13248
RAM 位總計: 368640
輸入/輸出數(shù): 311
門數(shù): 700000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 400-BGA
供應(yīng)商設(shè)備封裝: 400-FBGA(21x21)
XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
46
Suspend Mode Timing
X-Ref Target - Figure 10
Figure 10: Suspend Mode Timing
Table 43: Suspend Mode Timing Parameters
Symbol
Description
Min
Typ
Max
Units
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
(suspend_filter:No)
–7
–ns
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch filter
enabled (suspend_filter:Yes)
+160
+300
+600
ns
TSUSPEND_GTS
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
–10
–ns
TSUSPEND_GWE
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
–<5
–ns
TSUSPEND_DISABLE
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled
340
–ns
Exiting Suspend Mode
TSUSPENDLOW_AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not
include DCM lock time.
4 to 108
–s
TSUSPEND_ENABLE
Falling edge of the SUSPEND pin to FPGA input pins and interconnect
re-enabled
3.7 to 109
–s
TAWAKE_GWE1
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.
–67
–ns
TAWAKE_GWE512
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.
–14
–s
TAWAKE_GTS1
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.
–57
–ns
TAWAKE_GTS512
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and
sw_gts_cycle:512.
–14
–s
Notes:
1.
These parameters based on characterization.
2.
For information on using the Spartan-3A Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.
DS681_09_041111
Blocked
t
SUSPEND_DISABLE
t
SUSPEND_GWE
t
SUSPENDHIGH_AWAKE
t
AWAKE_GWE
t
AWAKE_GTS
t
SUSPEND_GTS
SUSPEND Input
AWAKE Output
Flip-Flops, Block RAM,
Distributed RAM
FPGA Outputs
FPGA Inputs,
Interconnect
Write Protected
Defined by SUSPEND constraint
Entering Suspend Mode
Exiting Suspend Mode
sw_gts_cycle
sw_gwe_cycle
t
SUSPEND_ENABLE
t
SUSPENDLOW_AWAKE
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