參數(shù)資料
型號: XA3S700A-4FGG400I
廠商: Xilinx Inc
文件頁數(shù): 52/57頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-3A 700K 400-FBGA
產(chǎn)品培訓(xùn)模塊: Extended Spartan 3A FPGA Family
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-3A XA
LAB/CLB數(shù): 1472
邏輯元件/單元數(shù): 13248
RAM 位總計(jì): 368640
輸入/輸出數(shù): 311
門數(shù): 700000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 400-BGA
供應(yīng)商設(shè)備封裝: 400-FBGA(21x21)
XA Spartan-3A Automotive FPGA Family Data Sheet
DS681 (v2.0) April 22, 2011
Product Specification
56
IEEE 1149.1/1532 JTAG Test Access Port Timing
X-Ref Target - Figure 16
Figure 16: JTAG Waveforms
Table 55: Timing for the JTAG Test Access Port
Symbol
Description
Speed Grade: -4
Units
Min
Max
Clock-to-Output Times
TTCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin
1.0
11.0
ns
Setup Times
TTDITCK
The time from the setup of data at the
TDI pin to the rising transition at the
TCK pin
All devices and functions except those shown below
7.0
–ns
Boundary scan commands (INTEST, EXTEST,
SAMPLE) on XA3S700A and XA3S1400A FPGAs
11.0
TTMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
7.0
–ns
Hold Times
TTCKTDI
The time from the rising transition at
the TCK pin to the point when data is
last held at the TDI pin
All functions except those shown below
0
–ns
Configuration commands (CFG_IN, ISC_PROGRAM)
2.0
TTCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
0
–ns
Clock Timing
TCCH
The High pulse width at the TCK pin
All functions except ISC_DNA command
5
–ns
TCCL
The Low pulse width at the TCK pin
5
–ns
TCCHDNA The High pulse width at the TCK pin
During ISC_DNA command
10
10,000
ns
TCCLDNA The Low pulse width at the TCK pin
10
10,000
ns
FTCK
Frequency of the TCK signal
All operations on XA3S200A and XA3S400A FPGAs
and for BYPASS or HIGHZ instructions on all FPGAs
033
MHz
All operations on XA3S700A and XA3S1400A FPGAs,
except for BYPASS or HIGHZ instructions
20
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
TCK
TTMSTCK
TMS
TDI
TDO
(Input)
(Output)
TTCKTMS
TTCKTDI
TTCKTDO
TTDITCK
DS681_15_041111
TCCH
TCCL
1/FTCK
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