- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4284 > XC2S100E-6FT256C (Xilinx Inc)IC FPGA 1.8V 600 CLB'S 256-FBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | XC2S100E-6FT256C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 36/108頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V 600 CLB'S 256-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-IIE |
| LAB/CLB數(shù)： | 600 |
| 邏輯元件/單元數(shù)： | 2700 |
| RAM 位總計(jì)： | 40960 |
| 輸入/輸出數(shù)： | 182 |
| 門數(shù)： | 100000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FTBGA |
| 其它名稱： | 122-1208 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)當(dāng)前第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)
DS077-3 (v3.0) August 9, 2013
33
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Power-On Requirements
Spartan-IIE FPGAs require that a minimum supply current
ICCPO be provided to the VCCINT lines for a successful
power-on. If more current is available, the FPGA can con-
sume more than ICCPO min., though this cannot adversely
affect reliability.
A maximum limit for ICCPO is not specified. Be careful when
using foldback/crowbar supplies and fuses. It is possible to
control the magnitude of ICCPO by limiting the supply current
available to the FPGA. A current limit below the trip level will
avoid inadvertently activating over-current protection cir-
cuits.
DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for VOL and VOH are guaranteed output voltages
over the recommended operating conditions. Only selected
standards are tested. These are chosen to ensure that all
standards meet their specifications. The selected standards
are tested at minimum VCCO with the respective IOL and IOH
currents shown. Other standards are sample tested.
Symbol
Description
Min(1)
Typ
Max
Units
ICCPO
Total VCCINT supply current
required during power-on
Commercial
XC2S50E - XC2S300E
After PCN(2)
300
-
mA
Before
PCN(2)
500
-
mA
XC2S400E - XC2S600E
500
-
mA
Industrial
XC2S50E - XC2S300E
After PCN(2)
500
-
mA
Before
PCN(2)
2
-
A
XC2S400E - XC2S600E
700
-
mA
TCCPO
VCCINT(3,4) ramp time
After PCN(2)
500
-
μs
Before PCN(2)
2
-
50
ms
IHSPO
AC current per pin during power-on in
hot-swap applications when
VIN > VCCO + 0.4V; duration < 10ns
After PCN(2)
-
±60
-
μA
Notes:
1.
The ICCPO requirement applies for a brief time (commonly only a few milliseconds) when VCCINT ramps from 0 to 1.8V.
2.
Devices built after the Product Change Notice PCN 2002-05 (see
http://www.xilinx.com/support/documentation/customer_notices/pcn2002-05.pdf) have improved power-on requirements. Devices
after the PCN have a ‘T’ preceding the date code as referenced in the PCN. Note that the XC2S150E, XC2S400E, and XC2S600E
always have this mark. Devices before the PCN have an ‘S’ preceding the date code. Note that devices before the PCN are
measured with VCCINT and VCCO powering up simultaneously.
3.
The ramp time is measured from GND to 1.8V on a fully loaded board.
4.
VCCINT must not dip in the negative direction during power on.
5.
I/Os are not guaranteed to be disabled until VCCINT is applied.
6.
For more information on designing to meet the power-on specifications, refer to the application note XAPP450 "Power-On Current
Input/Output
Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
LVTTL(1)
–0.5
0.8
2.0
3.6
0.4
2.4
24
–24
LVCMOS2
–0.5
0.7
1.7
2.7
0.4
1.9
12
–12
LVCMOS18
–0.5
35% VCCO
65% VCCO
1.95
0.4
VCCO – 0.4
8
–8
PCI, 3.3V
–0.5
30% VCCO
50% VCCO
VCCO + 0.5
10% VCCO
90% VCCO
Note (2)
GTL
–0.5
VREF – 0.05
VREF + 0.05
3.6
0.4
-
40
-
GTL+
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.6
-
36
-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ABB91DHFT-S578 | EDGECARD 182POS .050 SMD W/POSTS |
| 24FC64FT-I/ST | IC EEPROM 64KBIT 1MHZ 8TSSOP |
| 24FC64FT-I/MS | IC EEPROM 64KBIT 1MHZ 8MSOP |
| 24LC64FT-E/OT | IC SRL EEPROM 8KX8 2.5V SOT23-5 |
| XC3S700A-4FT256I | IC FPGA SPARTAN 3 256FTBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S100E6FT256I | 制造商:Xilinx 功能描述: |
| XC2S100E-6FT256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S100E-6FTG256C | 功能描述:IC SPARTAN-IIE FPGA 100K 256FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC2S100E-6FTG256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S100E-6PQ208C | 功能描述:IC FPGA 1.8V 600 CLB'S 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。