- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19312 > XC2S50E-6PQG208C (Xilinx Inc)IC SPARTAN-IIE FPGA 50K 208-PQFP PDF資料下載
參數(shù)資料
| 型號： | XC2S50E-6PQG208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 28/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPARTAN-IIE FPGA 50K 208-PQFP |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標準包裝： | 24 |
| 系列： | Spartan®-IIE |
| LAB/CLB數(shù)： | 384 |
| 邏輯元件/單元數(shù)： | 1728 |
| RAM 位總計： | 32768 |
| 輸入/輸出數(shù)： | 146 |
| 門數(shù)： | 50000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 其它名稱： | 122-1330 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁
26
DS077-2 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Master Serial Mode
In Master Serial mode, the CCLK output of the FPGA drives
a Xilinx PROM, which feeds a serial stream of configuration
data to the FPGA’s DIN input. Figure 19 shows a Master
Serial FPGA configuring a Slave Serial FPGA from a
PROM. A Spartan-IIE device in Master Serial mode should
be connected as shown for the device on the left side. Mas-
ter Serial mode is selected by a <00x> on the mode pins
(M0, M1, M2). The PROM RESET pin is driven by INIT, and
the CE input is driven by DONE. For more information on
serial PROMs, see the Xilinx Configuration PROM data
sheets at www.xilinx.com.
The interface is identical to the slave serial mode except
that an oscillator internal to the FPGA is used to generate
the configuration clock (CCLK). Any of a number of different
frequencies ranging from 4 to 60 MHz can be set using the
ConfigRate option in the Xilinx development software.
When selecting a CCLK frequency, ensure that the serial
PROM and any daisy-chained FPGAs are fast enough to
support the clock rate. On power-up, while the first 60 bytes
of the configuration data are being loaded, the CCLK fre-
quency is always 2.5 MHz. This frequency is used until the
ConfigRate bits, part of the configuration file, have been
loaded into the FPGA, at which point the frequency
changes to the selected ConfigRate. Unless a different fre-
quency is specified in the design, the default ConfigRate is
4 MHz. The frequency of the CCLK signal created by the
internal oscillator has a variance of +45%, –30% from the
specified value.
The FPGA accepts one bit of configuration data on each ris-
ing CCLK edge. After the FPGA has been loaded, the data
for the next device in a daisy-chain is presented on the
DOUT pin after the rising CCLK edge. The timing for Master
Serial mode is shown in Figure 25, page 49.
Slave Parallel Mode (SelectMAP)
The Slave Parallel mode, also known as SelectMAP, is the
fastest configuration option. Byte-wide data is written into
the FPGA on the D0-D7 pins. Note that D0 is the MSB of
each byte for configuration. A BUSY flag is provided for con-
trolling the flow of data at a clock frequency above 50 MHz.
shows
the
connections
for
two
Spartan-IIE devices using the Slave Parallel mode. Slave
Parallel mode is selected by a <011> on the mode pins (M0,
M1, M2).
The agent controlling configuration is not shown. Typically, a
processor, a microcontroller, or CPLD controls the Slave
Parallel interface. The controlling agent provides byte-wide
configuration data, CCLK, a Chip Select (CS) signal and a
Write signal (WRITE). If BUSY is asserted (High) by the
FPGA, the data must be held until BUSY goes Low.
After configuration, the pins of the Slave Parallel port
(D0-D7) can be used as additional user I/O. Alternatively,
the port may be retained to permit high-speed 8-bit read-
back. Then data can be read by deasserting WRITE. If
retention is selected, prohibit the D0-D7 pins from being
used as user I/O. See Readback, page 28.
相關PDF資料 |
PDF描述 |
|---|---|
| AIMC-0805-R12J-T | INDUCTOR MULTILAYER 120NH 0805 |
| XC3S200-4VQG100I | SPARTAN-3 FPGA 200K STD 100VQFP |
| XC3S200A-4VQG100I | IC FPGA SPARTAN-3A 200K 100-VQFP |
| GBM10DCSN | CONN EDGECARD 20POS DIP .156 SLD |
| GBM10DCSH | CONN EDGECARD 20POS DIP .156 SLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S50E-6PQG208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S50E-6TQ144C | 功能描述:IC FPGA 1.8V 384 CLB'S 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-IIE 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
| XC2S50E-6TQ144I | 制造商:Xilinx 功能描述:IC SYSTEM GATE |
| XC2S50E-6TQ144Q | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
| XC2S50E-6TQG144C | 功能描述:IC SPARTAN-IIE FPGA 50K 144-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-IIE 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
發(fā)布緊急采購，3分鐘左右您將得到回復。