參數(shù)資料
型號(hào)： XC2S50E-6PQG208C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 29/108頁(yè)
文件大?。?/td> 0K
描述： IC SPARTAN-IIE FPGA 50K 208-PQFP
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 24
系列： Spartan®-IIE
LAB/CLB數(shù)： 384
邏輯元件/單元數(shù)： 1728
RAM 位總計(jì)： 32768
輸入/輸出數(shù)： 146
門數(shù)： 50000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
其它名稱： 122-1330
DS077-2 (v3.0) August 9, 2013
27
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Multiple Spartan-IIE FPGAs can be configured using the
Slave Parallel mode, and be made to start-up simultane-
ously. To configure multiple devices in this way, wire the indi-
vidual CCLK, Data, WRITE, and BUSY pins of all the
devices in parallel. The individual devices are loaded sepa-
rately by asserting the CS pin of each device in turn and
writing the appropriate data. Sync-to-DONE start-up timing
is used to ensure that the start-up sequence does not begin
until all the FPGAs have been loaded. See Start-up,
Write
When using the Slave Parallel Mode, write operations send
packets of byte-wide configuration data into the FPGA.
Figure 21, page 28 shows a flowchart of the write sequence
used to load data into the Spartan-IIE FPGA. This is an
expansion of the "Load Configuration Data Frames" block in
The timing for Slave Parallel mode is shown in Figure 26,
For the present example, the user holds WRITE and CS
Low throughout the sequence of write operations. Note that
when CS is asserted on successive CCLKs, WRITE must
remain either asserted or deasserted. Otherwise an abort
will be initiated, as in the next section.
1.
Drive data onto D0-D7. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more than one device’s CS should be asserted.
2.
On the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance will instead
occur on the first clock after BUSY goes Low, and the
data must be held until this happens.
3.
Repeat steps 1 and 2 until all the data has been sent.
4.
Deassert CS and WRITE.
Figure 20: Slave Parallel Configuration Circuit Diagram
M1 M2
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE
INIT
CCLK
DATA[7:0]
WRITE
BUSY
CS(0)
Spartan-IIE
DONE
INIT
PROGRAM
M1 M2
M0
D0:D7
CCLK
WRITE
BUSY
CS
PROGRAM
DONE
INIT
CS(1)
Spartan-IIE
DS077-2_06_110102
GND
相關(guān)PDF資料
PDF描述
AIMC-0805-R12J-T INDUCTOR MULTILAYER 120NH 0805
XC3S200-4VQG100I SPARTAN-3 FPGA 200K STD 100VQFP
XC3S200A-4VQG100I IC FPGA SPARTAN-3A 200K 100-VQFP
GBM10DCSN CONN EDGECARD 20POS DIP .156 SLD
GBM10DCSH CONN EDGECARD 20POS DIP .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S50E-6PQG208I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S50E-6TQ144C 功能描述:IC FPGA 1.8V 384 CLB'S 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC2S50E-6TQ144I 制造商:Xilinx 功能描述:IC SYSTEM GATE
XC2S50E-6TQ144Q 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述:
XC2S50E-6TQG144C 功能描述:IC SPARTAN-IIE FPGA 50K 144-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*