參數(shù)資料
型號： XC2S600E-6FG456Q
廠商： Xilinx Inc
文件頁數(shù)： 14/108頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-IIE 456FPBGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標準包裝： 60
系列： Spartan®-IIE
LAB/CLB數(shù)： 3456
邏輯元件/單元數(shù)： 15552
RAM 位總計： 294912
輸入/輸出數(shù)： 329
門數(shù)： 600000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 125°C
封裝/外殼： 456-BBGA
供應商設備封裝： 456-FBGA
DS077-2 (v3.0) August 9, 2013
13
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Configurable Logic Block
The basic building block of the Spartan-IIE FPGA CLB is the
logic cell (LC). An LC includes a 4-input function generator,
carry logic, and storage element. The output from the func-
tion generator in each LC drives the CLB output or the
D input of the flip-flop. Each Spartan-IIE FPGA CLB con-
tains four LCs, organized in two similar slices; a single slice
is shown in Figure 6.
In addition to the four basic LCs, the Spartan-IIE FPGA CLB
contains logic that combines function generators to provide
functions of five or six inputs.
Look-Up Tables
Spartan-IIE FPGA function generators are implemented as
4-input look-up tables (LUTs). In addition to operating as a
function generator, each LUT can provide a 16 x 1-bit syn-
chronous RAM. Furthermore, the two LUTs within a slice
can be combined to create a 16 x 2-bit or 32 x 1-bit syn-
chronous RAM, or a 16 x 1-bit dual-port synchronous RAM.
The Spartan-IIE FPGA LUT can also provide a 16-bit shift
register that is ideal for capturing high-speed or burst-mode
data. This mode can also be used to store data in applica-
tions such as Digital Signal Processing.
Storage Elements
Storage elements in the Spartan-IIE FPGA slice can be
configured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D inputs can be driven either by
function generators within the slice or directly from slice
inputs, bypassing the function generators.
In addition to Clock and Clock Enable signals, each slice
has synchronous set and reset signals (SR and BY). SR
forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals may be configured to
operate asynchronously.
All control signals are independently invertible, and are
shared by the two flip-flops within the slice.
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