參數(shù)資料
型號(hào): XC2S600E-6FG456Q
廠商: Xilinx Inc
文件頁(yè)數(shù): 98/108頁(yè)
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-IIE 456FPBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-IIE
LAB/CLB數(shù): 3456
邏輯元件/單元數(shù): 15552
RAM 位總計(jì): 294912
輸入/輸出數(shù): 329
門數(shù): 600000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 456-BBGA
供應(yīng)商設(shè)備封裝: 456-FBGA
DS077-2 (v3.0) August 9, 2013
9
Product Specification
2001-2013 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Architectural Description
Spartan-IIE FPGA Array
The Spartan-IIE user-programmable gate array, shown in
Figure 3, is composed of five major configurable elements:
IOBs provide the interface between the package pins
and the internal logic
CLBs provide the functional elements for constructing
most logic
Dedicated block RAM memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
Versatile multi-level interconnect structure
As can be seen in Figure 3, the CLBs form the central logic
structure with easy access to all support and routing struc-
tures. The IOBs are located around all the logic and mem-
ory elements for easy and quick routing of signals on and off
the chip.
Values stored in static memory cells control all the configu-
rable logic elements and interconnect resources. These val-
ues load into the memory cells on power-up, and can reload
if necessary to change the function of the device.
Each of these elements will be discussed in detail in the fol-
lowing sections.
Spartan-IIE FPGA Family:
Functional Description
DS077-2 (v3.0) August 9, 2013
0
Product Specification
R
Figure 3: Basic Spartan-IIE Family FPGA Block Diagram
DLL
BLOCK
RAM
BLOCK
RAM
BLOCK
RAM
BLOCK
RAM
I/O LOGIC
CLBs
DS077_01_052102
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