參數(shù)資料
型號: XC2S600E-6FG456Q
廠商: Xilinx Inc
文件頁數(shù): 37/108頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN-IIE 456FPBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-IIE
LAB/CLB數(shù): 3456
邏輯元件/單元數(shù): 15552
RAM 位總計: 294912
輸入/輸出數(shù): 329
門數(shù): 600000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 456-BBGA
供應(yīng)商設(shè)備封裝: 456-FBGA
34
DS077-3 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
LVDS DC Specifications
LVPECL DC Specifications
These values are valid at the output of the source termina-
tion pack shown under LVPECL, with a 100
Ω differential
load only. The VOH levels are 200 mV below standard
LVPECL levels and are compatible with devices tolerant of
lower common-mode ranges. The following table summa-
rizes the DC output specifications of LVPECL.
HSTL I
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
8
–8
HSTL III
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
24
–8
HSTL IV
–0.5
VREF – 0.1
VREF + 0.1
3.6
0.4
VCCO – 0.4
48
–8
SSTL3 I
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.6
VREF + 0.6
8
–8
SSTL3 II
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.8
VREF + 0.8
16
–16
SSTL2 I
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.61 VREF + 0.61
7.6
–7.6
SSTL2 II
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.8
VREF + 0.8
15.2
–15.2
CTT
–0.5
VREF – 0.2
VREF + 0.2
3.6
VREF – 0.4
VREF + 0.4
8
–8
AGP
–0.5
VREF – 0.2
VREF + 0.2
3.6
10% VCCO
90% VCCO
Note (2)
Notes:
1.
VOL and VOH for lower drive currents are sample tested.
2.
Tested according to the relevant specifications.
Symbol
Description
Conditions
Min
Typ
Max
Units
VCCO
Supply voltage
2.375
2.5
2.625
V
VOH
Output High voltage for Q and Q
RT = 100Ω across Q and Q signals
1.25
1.425
1.6
V
VOL
Output Low voltage for Q and Q
RT = 100Ω across Q and Q signals
0.9
1.075
1.25
V
VODIFF
Differential output voltage (Q – Q),
Q = High or (Q – Q), Q = High
RT = 100Ω across Q and Q signals
250
350
450
mV
VOCM
Output common-mode voltage
RT = 100Ω across Q and Q signals
1.125
1.25
1.375
V
VIDIFF
Differential input voltage (Q – Q),
Q = High or (Q – Q), Q = High
Common-mode input voltage = 1.25 V
100
350
-
mV
VICM
Input common-mode voltage
Differential input voltage =
±350 mV
0.2
1.25
2.2
V
Input/Output
Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
DC Parameter
Min
Max
Min
Max
Min
Max
Units
VCCO
3.0
3.3
3.6
V
VOH
1.8
2.11
1.92
2.28
2.13
2.41
V
VOL
0.96
1.27
1.06
1.43
1.30
1.57
V
VIH
1.49
2.72
1.49
2.72
1.49
2.72
V
VIL
0.86
2.125
0.86
2.125
0.86
2.125
V
Differential input voltage
0.3
-
0.3
-
0.3
-
V
相關(guān)PDF資料
PDF描述
XC2V8000-5FFG1152I IC FPGA VIRTEX-II 8M 1152-FBGA
XC3195A-09PQ160C IC FPGA 7500 GATE 160-PQFP
XC3S1000L-4FGG320C SPARTAN-3A FPGA 1M STD 320-FBGA
XC3S1400A-4FT256I IC FPGA SPARTAN 3 256FTBGA
XC3S1400A-5FGG676C IC SPARTAN-3A FPGA 1400K 676FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC2S600E-6FG676C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
XC2S600E-6FG676I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S600E-6FGG456C 功能描述:IC SPARTAN-IIE FPGA 600K 456FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Spartan®-IIE 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC2S600E-6FGG456I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA
XC2S600E-6FGG676C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA