參數(shù)資料
型號: XC2S600E-6FG456Q
廠商: Xilinx Inc
文件頁數(shù): 44/108頁
文件大小: 0K
描述: IC FPGA SPARTAN-IIE 456FPBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標準包裝: 60
系列: Spartan®-IIE
LAB/CLB數(shù): 3456
邏輯元件/單元數(shù): 15552
RAM 位總計: 294912
輸入/輸出數(shù): 329
門數(shù): 600000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 125°C
封裝/外殼: 456-BBGA
供應商設(shè)備封裝: 456-FBGA
40
DS077-3 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
IOB Output Delay Adjustments for Different Standards(1)
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown. A delay adjusted in this way constitutes a worst-case limit.
Symbol
Description
Standard
Speed Grade
Units
-7
-6
Output Delay Adjustments (Adj)
TOLVTTL_S2
Standard-specific adjustments for
output delays terminating at pads
(based on standard capacitive
load, CSL)
LVTTL, Slow, 2 mA
14.7
ns
TOLVTTL_S4
4 mA
7.5
ns
TOLVTTL_S6
6 mA
4.8
ns
TOLVTTL_S8
8 mA
3.0
ns
TOLVTTL_S12
12 mA
1.9
ns
TOLVTTL_S16
16 mA
1.7
ns
TOLVTTL_S24
24 mA
1.3
ns
TOLVTTL_F2
LVTTL, Fast, 2 mA
13.1
ns
TOLVTTL_F4
4 mA
5.3
ns
TOLVTTL_F6
6 mA
3.1
ns
TOLVTTL_F8
8 mA
1.0
ns
TOLVTTL_F12
12 mA
0
ns
TOLVTTL_F16
16 mA
–0.05
ns
TOLVTTL_F24
24 mA
–0.20
ns
TOLVCMOS2
LVCMOS2
0.09
ns
TOLVCMOS18
LVCMOS18
0.7
ns
TOLVDS
LVDS
–1.2
ns
TOLVPECL
LVPECL
–0.41
ns
TOPCI33_3
PCI, 33 MHz, 3.3V
2.3
ns
TOPCI66_3
PCI, 66 MHz, 3.3V
–0.41
ns
TOGTL
GTL
0.49
ns
TOGTLP
GTL+
0.8
ns
TOHSTL_I
HSTL I
–0.51
ns
TOHSTL_III
HSTL III
–0.91
ns
TOHSTL_IV
HSTL IV
–1.01
ns
TOSSTL2_I
SSTL2 I
–0.51
ns
TOSSLT2_II
SSTL2 II
–0.91
ns
TOSSTL3_I
SSTL3 I
–0.51
ns
TOSSTL3_II
SSTL3 II
–1.01
ns
TOCTT
CTT
–0.61
ns
TOAGP
AGP
–0.91
ns
Notes:
1.
Output timing is measured at 1.4V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see the
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