Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics
DS077-3 (v2.0) November 18, 2002
Product Specification
www.xilinx.com
1-800-255-7778
15
R
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Symbol
Description
Speed Grade
Units
-7
-6
Min
Max
Min
Max
Combinatorial Delays
T
ILO
T
IF5
T
IF5X
T
IF6Y
T
F5INY
T
IFNCTL
4-input function: F/G inputs to X/Y outputs
0.18
0.42
0.18
0.47
ns
5-input function: F/G inputs to F5 output
0.3
0.8
0.3
0.9
ns
5-input function: F/G inputs to X output
0.3
0.8
0.3
0.9
ns
6-input function: F/G inputs to Y output via F6 MUX
0.3
0.9
0.3
1.0
ns
6-input function: F5IN input to Y output
0.04
0.2
0.04
0.22
ns
Incremental delay routing through transparent latch to
XQ/YQ outputs
-
0.7
-
0.8
ns
T
BYYB
BY input to YB output
0.18
0.46
0.18
0.51
ns
Sequential Delays
T
CKO
T
CKLO
FF clock CLK to XQ/YQ outputs
0.3
0.9
0.3
1.0
ns
Latch clock CLK to XQ/YQ outputs
0.3
0.9
0.3
1.0
ns
Setup/Hold Times with Respect to Clock CLK
T
ICK
/ T
CKI
T
IF5CK
/ T
CKIF5
T
F5INCK
/ T
CKF5IN
6-input function: F5IN input
T
IF6CK
/ T
CKIF6
6-input function: F/G inputs via F6 MUX
T
DICK
/ T
CKDI
BX/BY inputs
T
CECK
/ T
CKCE
CE input
T
RCK
/ T
CKR
SR/BY inputs (synchronous)
Clock CLK
4-input function: F/G inputs
1.0 / 0
-
1.1 / 0
-
ns
5-input function: F/G inputs
1.4 / 0
-
1.5 / 0
-
ns
0.8 / 0
-
0.8 / 0
-
ns
1.5 / 0
-
1.6 / 0
-
ns
0.7 / 0
-
0.8 / 0
-
ns
0.7 / 0
-
0.7 / 0
-
ns
0.52 / 0
-
0.6 / 0
-
ns
T
CH
T
CL
Pulse width, High
1.3
-
1.4
-
ns
Pulse width, Low
1.3
-
1.4
-
ns
Set/Reset
T
RPW
T
RQ
Pulse width, SR/BY inputs
2.1
-
2.4
-
ns
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
0.3
0.9
0.3
1.0
ns
F
TOG
Toggle frequency (for export control)
-
400
-
357
MHz