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參數(shù)資料
| 型號： | XC2S600E-7FG676C |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 183K |
| 代理商： | XC2S600E-7FG676C |
Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics
DS077-3 (v2.0) November 18, 2002
Product Specification
www.xilinx.com
1-800-255-7778
5
R
Switching Characteristics
Internal timing parameters are derived from measuring
internal test patterns. Listed below are representative val-
ues. For more specific, more precise, and worst-case guar-
anteed data, use the values reported by the static timing
analyzer (TRACE in the Xilinx Development System) and
back-annotated to the simulation netlist. All timing parame-
ters assume worst-case operating conditions (supply volt-
age and junction temperature). Values apply to all
Spartan-IIE devices unless otherwise noted.
Global Clock Input to Output Delay for LVTTL,
with
DLL (Pin-to-Pin)
(1)
Global Clock Input to Output Delay for LVTTL,
without
DLL (Pin-to-Pin)
(1)
Symbol
Description
Speed Grade
Units
All
-7
-6
Min
Max
Max
T
ICKOFDLL
LVTTL global clock input to output delay using
output flip-flop for LVTTL, 12 mA, fast slew rate,
with
DLL.
1.0
3.1
3.1
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 50% V
threshold with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the
Min values. For other I/O standards and different loads, see the tables
Constants for Calculating T
IOOP
and
Delay Measurement
Methodology
, page 11
.
DLL output jitter is already included in the timing calculation.
For data
output
with different standards, adjust delays with the values shown in
IOB Output Delay Adjustments for Different
Standards(1)
, page 10
. For a global clock input with standards other than LVTTL, adjust delays with values from the
I/O Standard
Global Clock Input Adjustments
, page 12
.
2.
3.
4.
Symbol
Description
Device
Speed Grade
Units
All
-7
-6
Min
Max
Max
T
ICKOF
LVTTL global clock input to output
delay using output flip-flop for
LVTTL, 12 mA, fast slew rate,
without
DLL.
XC2S50E
1.5
4.4
4.6
ns
XC2S100E
1.5
4.4
4.6
ns
XC2S150E
1.5
4.5
4.7
ns
XC2S200E
1.5
4.5
4.7
ns
XC2S300E
1.5
4.5
4.7
ns
XC2S400E
1.5
4.6
4.8
ns
XC2S600E
1.6
4.7
4.9
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Output timing is measured at 50% V
threshold with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the
Min values. For other I/O standards and different loads, see the tables
Constants for Calculating T
IOOP
and
Delay Measurement
Methodology
, page 11
.
For data
output
with different standards, adjust delays with the values shown in
IOB Output Delay Adjustments for Different
Standards(1)
, page 10
. For a global clock input with standards other than LVTTL, adjust delays with values from the
I/O Standard
Global Clock Input Adjustments
, page 12
.
2.
3.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S600E-7FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S600E-7FGG456C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S600E-7FGG456I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S600E-7FGG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S600E-7FGG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
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