參數(shù)資料
型號: XC3S400AN-4FTG256I
廠商: Xilinx Inc
文件頁數(shù): 37/123頁
文件大小: 0K
描述: IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-3AN
LAB/CLB數(shù): 896
邏輯元件/單元數(shù): 8064
RAM 位總計(jì): 368640
輸入/輸出數(shù): 195
門數(shù): 400000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
20
Differential Output Pairs
DIFF_SSTL3_II(8)
3.0
3.3
3.6
100
–1.1
–1.9
Notes:
1.
The VCCO rails supply only differential output drivers, not input circuits.
2.
VICM must be less than VCCAUX.
3.
These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the “Using I/O Resources”
chapter in UG331.
4.
5.
LVPECL is supported on inputs only, not outputs. Requires VCCAUX = 3.3V ± 10%.
6.
LVPECL_33 maximum VICM =VCCAUX –(VID / 2)
7.
Requires VCCAUX = 3.3V ± 10% for inputs. (VCCAUX – 300 mV) VICM (VCCAUX – 37 mV)
8.
VREF inputs are used for the DIFF_SSTL and DIFF_HSTL standards. The VREF settings are the same as for the single-ended versions in
Table 13. Other differential standards do not use VREF.
9.
These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the “Using I/O Resources”
chapter in UG331.
X-Ref Target - Figure 7
Figure 7: Differential Output Voltages
Table 15: Recommended Operating Conditions for User I/Os Using Differential Signal Standards (Cont’d)
IOSTANDARD Attribute
VCCO for Drivers(1)
VID
VICM(2)
Min (V)
Nom (V)
Max (V)
Min (mV)
Nom (mV) Max (mV)
Min (V)
Nom (V)
Max (V)
V
OUTN
V
OUTP
GND level
50%
V
OCM
V
OCM
V
OD
V
OL
V
OH
V
OUTP
Internal
Logic
V
OUTN
N
P
= Output common mode voltage =
2
V
OUTP +VOUTN
V
OD = Output differential voltage =
V
OH = Output voltage indicating a High logic level
V
OL
= Output voltage indicating a Low logic level
V
OUTP -VOUTN
Differential
I/O Pair Pins
DS529-3_11_082810
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