參數(shù)資料
型號(hào)： XC3S400AN-4FTG256I
廠商： Xilinx Inc
文件頁數(shù)： 43/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 896
邏輯元件/單元數(shù)： 8064
RAM 位總計(jì)： 368640
輸入/輸出數(shù)： 195
門數(shù)： 400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
26
Pin-to-Pin Setup and Hold Times
Table 22: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Symbol
Description
Conditions
Device
Speed Grade
Units
-5
-4
Min
Setup Times
TPSDCM
When writing to the Input
Flip-Flop (IFF), the time from the
setup of data at the Input pin to
the active transition at a Global
Clock pin. The DCM is in use. No
Input Delay is programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 0,
with DCM(4)
XC3S50AN
2.45
2.68
ns
XC3S200AN
2.59
2.84
ns
XC3S400AN
2.38
2.68
ns
XC3S700AN
2.38
2.57
ns
XC3S1400AN
1.91
2.17
ns
TPSFD
When writing to IFF, the time from
the setup of data at the Input pin
to an active transition at the
Global Clock pin. The DCM is not
in use. The Input Delay is
programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 5,
without DCM
XC3S50AN
2.55
2.76
ns
XC3S200AN
2.32
2.76
ns
XC3S400AN
2.21
2.60
ns
XC3S700AN
2.28
2.63
ns
XC3S1400AN
2.33
2.41
ns
Hold Times
TPHDCM
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is in use. No Input Delay is
programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 0,
with DCM(4)
XC3S50AN
–0.36
ns
XC3S200AN
–0.52
ns
XC3S400AN
–0.33
–0.29
ns
XC3S700AN
–0.17
–0.12
ns
XC3S1400AN
–0.07
0.00
ns
TPHFD
When writing to IFF, the time from
the active transition at the Global
Clock pin to the point when data
must be held at the Input pin. The
DCM is not in use. The Input
Delay is programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 5,
without DCM
XC3S50AN
–0.63
–0.58
ns
XC3S200AN
–0.56
ns
XC3S400AN
–0.42
ns
XC3S700AN
–0.80
–0.75
ns
XC3S1400AN
–0.69
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
2.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 26. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
3.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 26. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
4.
DCM output jitter is included in all measurements.
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