參數(shù)資料
型號(hào)： XC3S400AN-4FTG256I
廠商： Xilinx Inc
文件頁數(shù)： 65/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 896
邏輯元件/單元數(shù)： 8064
RAM 位總計(jì)： 368640
輸入/輸出數(shù)： 195
門數(shù)： 400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
46
LVCMOS12
Slow
2
17
40
4
–13
–25
6
–10
–18
Fast
2
12
9
31
4
–9
–13
6
–9
QuietIO
2
36
55
4
–33
–36
6
–27
–36
PCI33_3
9
16
PCI66_3
–9
–13
HSTL_I
–11
–20
HSTL_III
–7
–8
HSTL_I_18
13
17
HSTL_II_18
–5
HSTL_III_18
8
10
8
SSTL18_I
7
13
7
15
SSTL18_II
–9
SSTL2_I
10
18
SSTL2_II
–6
–9
SSTL3_I
7
8
10
SSTL3_II
5
6
7
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
8
–22
–
LVDS_33
8
–27
–
BLVDS_25
1
4
MINI_LVDS_25
8
–22
–
MINI_LVDS_33
8
–27
–
LVPECL_25
Input Only
LVPECL_33
Input Only
RSDS_25
8
–22
–
RSDS_33
8
–27
–
TMDS_33
8
–27
–
PPDS_25
8
–22
–
Table 32: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair (Cont’d)
Signal Standard
(IOSTANDARD)
Package Type
TQG144
FTG256,
FGG400,
FGG484,
FGG676
Top,
Bottom
Banks 0,2
Left,
Right
Banks 1,3
Top,
Bottom
Banks 0,2
Left,
Right
Banks 1,3
PPDS_33
8
–27
–
DIFF_HSTL_I
–5
–10
DIFF_HSTL_III
–3
–4
DIFF_HSTL_I_18
6
8
DIFF_HSTL_II_18
–2
DIFF_HSTL_III_18
4
5
4
DIFF_SSTL18_I
3
6
3
7
DIFF_SSTL18_II
–4
DIFF_SSTL2_I
5
9
DIFF_SSTL2_II
–3
–4
DIFF_SSTL3_I
3
4
5
DIFF_SSTL3_II
2
3
Notes:
1.
Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS, RSDS,
PPDS, miniLVDS, and TMDS, are only supported in top or bottom
banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
2.
The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the VIL/VIH voltage
limits for the respective I/O standard.
3.
If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
Table 32: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair (Cont’d)
Signal Standard
(IOSTANDARD)
Package Type
TQG144
FTG256,
FGG400,
FGG484,
FGG676
Top,
Bottom
Banks 0,2
Left,
Right
Banks 1,3
Top,
Bottom
Banks 0,2
Left,
Right
Banks 1,3
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