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參數(shù)資料
| 型號： | XC3S5000-4FGG676I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 21/272頁 |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 5M STD 676-FBGA |
| 產品培訓模塊： | Extended Spartan 3A FPGA Family |
| 標準包裝： | 40 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 8320 |
| 邏輯元件/單元數(shù)： | 74880 |
| RAM 位總計： | 1916928 |
| 輸入/輸出數(shù)： | 489 |
| 門數(shù)： | 5000000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 676-BGA |
| 供應商設備封裝： | 676-FBGA（27x27） |
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Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013
Product Specification
117
CCLK: Configuration Clock
The configuration clock signal on this pin synchronizes the reading or writing of configuration data. The CCLK pin is an
input-only pin for the Slave Serial and Slave Parallel configuration modes. In the Master Serial and Master Parallel
configuration modes, the FPGA drives the CCLK pin and CCLK should be treated as a full bidirectional I/O pin for signal
integrity analysis.
Although the CCLK frequency is relatively low, Spartan-3 FPGA output edge rates are fast. Any potential signal integrity
problems on the CCLK board trace can cause FPGA configuration to fail. Therefore, pay careful attention to the CCLK signal
integrity on the printed circuit board. Signal integrity simulation with IBIS is recommended. For all configuration modes
except JTAG, consider the signal integrity at every CCLK trace destination, including the FPGA’s CCLK pin. For more details
on CCLK design considerations, see Chapter 2 of UG332, Spartan-3 Generation Configuration User Guide.
During configuration, the CCLK pin has a pull-up resistor to VCCAUX, regardless of the HSWAP_EN pin. After configuration,
the CCLK pin is pulled High to VCCAUX by default as defined by the CclkPin bitstream selection, although this behavior is
programmable. Any clocks applied to CCLK after configuration are ignored unless the bitstream option Persist is set to Yes,
which retains the configuration interface. Persist is set to No by default. However, if Persist is set to Yes, then all clock
edges are potentially active events, depending on the other configuration control signals.
The bitstream generator option ConfigRate determines the frequency of the internally-generated CCLK oscillator required
for the Master configuration modes. The actual frequency is approximate due to the characteristics of the silicon oscillator
and varies by up to 50% over the temperature and voltage range. By default, CCLK operates at approximately 6 MHz. Via
the ConfigRate option, the oscillator frequency is set at approximately 3, 6, 12, 25, or 50 MHz. At power-on, CCLK always
starts operation at its lowest frequency. The device does not start operating at the higher frequency until the ConfigRate
control bits are loaded during the configuration process.
PROG_B: Program/Configure Device
This asynchronous pin initiates the configuration or re-configuration processes. A Low-going pulse resets the configuration
logic, initializing the configuration memory. This initialization process cannot finish until PROG_B returns High. Asserting
PROG_B Low for an extended period delays the configuration process. At power-up, there is always a pull-up resistor to
VCCAUX on this pin, regardless of the HSWAP_EN input. After configuration, the bitstream generator option ProgPin
determines whether or not the pull-up resistor is present. By default, the ProgPin option retains the pull-up resistor.
After configuration, hold the PROG_B input High. Any Low-going pulse on PROG_B lasting 300 ns or longer restarts the
configuration process.
DONE: Configuration Done, Delay Start-Up Sequence
The FPGA produces a Low-to-High transition on this pin indicating that the configuration process is complete. The bitstream
generator option DriveDone determines whether this pin functions as a totem-pole output that can drive High or as an
open-drain output. If configured as an open-drain output—which is the default behavior—then a pull-up resistor is required
to produce a High logic level. There is a bitstream option that provides an internal pull-up resistor, otherwise an external
pull-up resistor is required.
The open-drain option permits the DONE lines of multiple FPGAs to be tied together, so that the common node transitions
High only after all of the FPGAs have completed configuration. Externally holding the open-drain DONE pin Low delays the
start-up sequence, which marks the transition to user mode.
Table 73: PROG_B Operation
PROG_B Input
Response
Power-up
Automatically initiates configuration process.
Low-going pulse
Initiate (re-)configuration process and continue to completion.
Extended Low
Initiate (re-)configuration process and stall process at step where configuration memory is cleared. Process is
stalled until PROG_B returns High.
1
If the configuration process is started, continue to completion. If configuration process is complete, stay in User
mode.
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| XC3S5000-4FGG900C | 功能描述:SPARTAN-3A FPGA 5M STD 900-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC3S5000-4FGG900I | 功能描述:SPARTAN-3A FPGA 5M STD 900-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3 產品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC3S5000-5FG1156C | 制造商:Xilinx 功能描述: |
| XC3S5000-5FG676C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 5M GATES 74880 CELLS 725MHZ 1.2V 676FBGA - Trays |
| XC3S5000-5FG900C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 5M GATES 74880 CELLS 725MHZ 1.2V 900FBGA - Trays |
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