參數(shù)資料
型號(hào)： XC3S500E-4FGG320I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 213/227頁(yè)
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3E 500K 320-FBGA
標(biāo)準(zhǔn)包裝： 84
系列： Spartan®-3E
LAB/CLB數(shù)： 1164
邏輯元件/單元數(shù)： 10476
RAM 位總計(jì)： 368640
輸入/輸出數(shù)： 232
門數(shù)： 500000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 320-BGA
供應(yīng)商設(shè)備封裝： 320-FBGA（19x19）
配用： 122-1536-ND - KIT STARTER SPARTAN-3E
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Spartan-3E FPGA Family: Functional Description
DS312 (v4.1) July 19, 2013
Product Specification
86
This addressing flexibility allows the FPGA to share the
parallel Flash PROM with an external or embedded
processor. Depending on the specific processor
architecture, the processor boots either from the top or
bottom of memory. The FPGA is flexible and boots from the
opposite end of memory from the processor. Only the
processor or the FPGA can boot at any given time. The
FPGA can configure first, holding the processor in reset or
the processor can boot first, asserting the FPGA’s PROG_B
pin.
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are
available as full-featured user-I/O pins.
Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins or High to
disable the pull-up resistors. The HSWAP control must
remain at a constant logic level throughout FPGA
configuration. After configuration, when the FPGA’s DONE
output goes High, the HSWAP pin is available as
full-featured user-I/O pin and is powered by the VCCO_0
supply.
The RDWR_B and CSI_B must be Low throughout the
configuration process. After configuration, these pins also
become user I/O.
In a single-FPGA application, the FPGA’s CSO_B and
CCLK pins are not used but are actively driving during the
configuration process. The BUSY pin is not used but also
actively drives during configuration and is available as a
user I/O after configuration.
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Furthermore, the
bidirectional SelectMAP configuration peripheral interface
(see Slave Parallel Mode) is available after configuration. To
continue using SelectMAP mode, set the Persist bitstream
generator option to Yes. An external host can then read and
verify configuration data.
The Persist option will maintain A20-A23 as configuration
pins although they are not used in SelectMAP mode.
P
Table 59: Byte-Wide Peripheral Interface (BPI) Connections
Pin Name
FPGA Direction
Description
During Configuration
After Configuration
HSWAP
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank VCCO input.
0: Pull-ups during configuration
1: No pull-ups
Drive at valid logic level throughout
configuration.
User I/O
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode. See Design
M2 = 0, M1 = 1. Set M0 = 0 to start
at address 0, increment
addresses. Set M0 = 1 to start at
address 0xFFFFFF and
decrement addresses. Sampled
when INIT_B goes High.
User I/O
CSI_B
Input
Chip Select Input. Active Low.
Must be Low throughout
configuration.
User I/O. If bitstream option
Persist=Yes, becomes
part of SelectMap parallel
peripheral interface.
RDWR_B
Input
Read/Write Control. Active Low
write enable. Read functionality
typically only used after
configuration, if bitstream option
Persist=Yes.
Must be Low throughout
configuration.
User I/O. If bitstream option
Persist=Yes, becomes
part of SelectMap parallel
peripheral interface.
LDC0
Output
PROM Chip Enable
Connect to PROM chip-select
input (CE#). FPGA drives this
signal Low throughout
configuration.
User I/O. If the FPGA does
not access the PROM after
configuration, drive this pin
High to deselect the
PROM. A[23:0], D[7:0],
LDC[2:1], and HDC then
become available as user
I/O.
LDC1
Output
PROM Output Enable
Connect to the PROM
output-enable input (OE#). The
FPGA drives this signal Low
throughout configuration.
User I/O
P
A
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