參數(shù)資料
型號： XC3S50AN-4FTG256I
廠商： Xilinx Inc
文件頁數(shù)： 70/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN-3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 176
邏輯元件/單元數(shù)： 1584
RAM 位總計： 55296
輸入/輸出數(shù)： 195
門數(shù)： 50000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
50
18 x 18 Embedded Multiplier Timing
Table 37: 18 x 18 Embedded Multiplier Timing
Symbol
Description
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Combinatorial Delay
TMULT
Combinational multiplier propagation delay from the A and B inputs
to the P outputs, assuming 18-bit inputs and a 36-bit product
(AREG, BREG, and PREG registers unused)
–4.36
–4.88
ns
Clock-to-Output Times
TMSCKP_P
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using the PREG
register(2,3)
–0.84
–1.30
ns
TMSCKP_A
TMSCKP_B
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using either the AREG
or BREG register(2,4)
–4.44
–4.97
ns
Setup Times
TMSDCK_P
Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(3)
3.56
–3.98
–ns
TMSDCK_A
Data setup time at the A input before the active transition at the CLK
when using the AREG input register(4)
0.00
–0.00
–ns
TMSDCK_B
Data setup time at the B input before the active transition at the CLK
when using the BREG input register(4)
0.00
–0.00
–ns
Hold Times
TMSCKD_P
Data hold time at the A or B input after the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)(3)
0.00
–0.00
–ns
TMSCKD_A
Data hold time at the A input after the active transition at the CLK
when using the AREG input register(4)
0.35
–0.45
–ns
TMSCKD_B
Data hold time at the B input after the active transition at the CLK
when using the BREG input register(4)
0.35
–0.45
–ns
Clock Frequency
FMULT
Internal operating frequency for a two-stage 18x18 multiplier using
the AREG and BREG input registers and the PREG output
0
280
0
250
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10.
2.
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
3.
The PREG register is typically used when inferring a single-stage multiplier.
4.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
5.
Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
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XC3S50AN-4TQ144I 功能描述:IC FPGA SPARTAN 3AN 144TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
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XC3S50AN-4TQG144CES 制造商:Xilinx 功能描述:
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XC3S50AN-4TQG144ICES 制造商:Xilinx 功能描述:
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