參數(shù)資料
型號(hào)： XC5210-6PQ208C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 17/73頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 324 CLB'S 208-PQFP
產(chǎn)品變化通告： XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝： 24
系列： XC5200
LAB/CLB數(shù)： 324
邏輯元件/單元數(shù)： 1296
輸入/輸出數(shù)： 164
門(mén)數(shù)： 16000
電源電壓： 4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
其它名稱(chēng)： 122-1149
R
XC5200 Series Field Programmable Gate Arrays
7-106
November 5, 1998 (Version 5.2)
Express Mode
Express mode is similar to Slave Serial mode, except the
data is presented in parallel format, and is clocked into the
target device a byte at a time rather than a bit at a time. The
data is loaded in parallel into eight different columns: it is
not internally serialized. Eight bits of configuration data are
loaded with every CCLK cycle, therefore this configuration
mode runs at eight times the data rate of the other six
modes. In this mode the XC5200 family is capable of sup-
porting a CCLK frequency of 10 MHz, which is equivalent to
an 80 MHz serial rate, because eight bits of configuration
data are being loaded per CCLK cycle. An XC5210 in the
Express mode, for instance, can be configured in about 2
ms. The Express mode does not support CRC error check-
ing, but does support constant-field error checking. A
length count is not used in Express mode.
In the Express configuration mode, an external signal
drives the CCLK input(s). The first byte of parallel configu-
ration data must be available at the D inputs of the FPGA
devices a short set-up time before the second rising CCLK
edge. Subsequent data bytes are clocked in on each con-
secutive rising CCLK edge. See Figure 38 on page 123.
Bitstream generation currently generates a bitstream suffi-
cient to program in all configuration modes except Express.
Extra CCLK cycles are necessary to complete the configu-
ration, since in this mode data is read at a rate of eight bits
per CCLK cycle instead of one bit per cycle. Normally the
entire start-up sequence requires a number of bits that is
equal to the number of CCLK cycles needed. An additional
five CCLKs (equivalent to 40 extra bits) will guarantee com-
pletion of configuration, regardless of the start-up options
chosen.
Multiple slave devices with identical configurations can be
wired with parallel D0-D7 inputs.
In this way, multiple
devices can be configured simultaneously.
Pseudo Daisy Chain
Multiple devices with different configurations can be con-
nected together in a pseudo daisy chain, provided that all of
the devices are in Express mode. A single combined bit-
stream is used to configure the chain of Express mode
devices, but the input data bus must drive D0-D7 of each
device. Tie High the CS1 pin of the first device to be config-
ured, or leave it floating in the XC5200 since it has an inter-
nal pull-up. Connect the DOUT pin of each FPGA to the
CS1 pin of the next device in the chain. The D0-D7 inputs
are wired to each device in parallel. The DONE pins are
wired together, with one or more internal DONE pull-ups
activated. Alternatively, a 4.7 k
external resistor can be
used, if desired. (See Figure 37 on page 122.) CCLK pins
are tied together.
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All devices in Express mode are synchronized to the DONE
pin.
User I/O for each device become active after the
DONE pin for that device goes High. (The exact timing is
determined by options to the bitstream generation soft-
ware.) Since the DONE pin is open-drain and does not
drive a High value, tying the DONE pins of all devices
together prevents all devices in the chain from going High
until the last device in the chain has completed its configu-
ration cycle.
The status pin DOUT is pulled LOW two internal-oscillator
cycles (nominally 1 MHz) after INIT is recognized as High,
and remains Low until the device’s configuration memory is
full. Then DOUT is pulled High to signal the next device in
the chain to accept the configuration data on the D7-D0
bus. All devices receive and recognize the six bytes of pre-
amble and length count, irrespective of the level on CS1;
but subsequent frame data is accepted only when CS1 is
High and the device’s configuration memory is not already
full.
Setting CCLK Frequency
For Master modes, CCLK can be generated in one of three
frequencies. In the default slow mode, the frequency is
nominally 1 MHz. In fast CCLK mode, the frequency is
nominally 12 MHz. In medium CCLK mode, the frequency
is nominally 6 MHz. The frequency range is -50% to +50%.
The frequency is selected by an option when running the
bitstream generation software. If an XC5200-Series Master
is driving an XC3000- or XC2000-family slave, slow CCLK
mode must be used. Slow mode is the default.
Output
Connected
to CCLK
OE/T
0
1
0
.
0
1
.
Reset
X5223
etc
Active Low Output
Active High Output
Figure 22: CCLK Generation for XC3000 Master
Driving an XC5200-Series Slave
Table 11: XC5200 Bitstream Format
Data Type
Value
Occurrences
Fill Byte
11111111
Once per bit-
stream
Preamble
11110010
Length Counter
COUNT(23:0)
Fill Byte
11111111
Product Obsolete or Under Obsolescence
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XC5210-6PQ208C0167 制造商:Xilinx 功能描述:
XC5210-6PQ208I 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA)
XC5210-6PQ240C 功能描述:IC FPGA 324 CLB'S 240-PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC5200 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC5210-6PQ240I 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA)
XC5210-6PQG208C 制造商:Xilinx 功能描述:
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