參數資料
| 型號： | XC5210-6PQ208C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 15/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 324 CLB'S 208-PQFP |
| 產品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 標準包裝： | 24 |
| 系列： | XC5200 |
| LAB/CLB數： | 324 |
| 邏輯元件/單元數： | 1296 |
| 輸入/輸出數： | 164 |
| 門數： | 16000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 其它名稱： | 122-1149 |
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R
XC5200 Series Field Programmable Gate Arrays
7-104
November 5, 1998 (Version 5.2)
Configuration
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func-
tional
operation
of
the
internal
blocks
and
their
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip.
XC5200-Series devices use several hundred bits of config-
uration data per CLB and its associated interconnects.
Each configuration bit defines the state of a static memory
cell that controls either a function look-up table bit, a multi-
plexer input, or an interconnect pass transistor. The devel-
opment system translates the design into a netlist file. It
automatically partitions, places and routes the logic and
generates the configuration data in PROM format.
Special Purpose Pins
Three configuration mode pins (M2, M1, M0) are sampled
prior to configuration to determine the configuration mode.
After configuration, these pins can be used as auxiliary I/O
connections. The development system does not use these
resources unless they are explicitly specified in the design
entry. This is done by placing a special pad symbol called
MD2, MD1, or MD0 instead of the input or output pad sym-
bol.
In XC5200-Series devices, the mode pins have weak
pull-up resistors during configuration. With all three mode
pins High, Slave Serial mode is selected, which is the most
popular configuration mode. Therefore, for the most com-
mon configuration mode, the mode pins can be left uncon-
nected. (Note, however, that the internal pull-up resistor
value can be as high as 100 k
.) After configuration, these
pins can individually have weak pull-up or pull-down resis-
tors, as specified in the design. A pull-down resistor value
of 3.3k
is recommended.
These pins are located in the lower left chip corner and are
near the readback nets. This location allows convenient
routing if compatibility with the XC2000 and XC3000 family
conventions of M0/RT, M1/RD is desired.
Configuration Modes
XC5200 devices have seven configuration modes. These
modes are selected by a 3-bit input code applied to the M2,
M1, and M0 inputs. There are three self-loading Master
modes, two Peripheral modes, and a Serial Slave mode,
Note :*Peripheral Synchronous can be considered byte-wide
Slave Parallel
which is used primarily for daisy-chained devices. The sev-
enth mode, called Express mode, is an additional slave
mode that allows high-speed parallel configuration. The
coding for mode selection is shown in Table 10.
Note that the smallest package, VQ64, only supports the
Master Serial, Slave Serial, and Express modes.A detailed
description of each configuration mode, with timing infor-
mation, is included later in this data sheet. During configu-
ration, some of the I/O pins are used temporarily for the
configuration process.
All pins used during configuration
are shown in Table 13 on page 124.
Master Modes
The three Master modes use an internal oscillator to gener-
ate a Configuration Clock (CCLK) for driving potential slave
devices. They also generate address and timing for exter-
nal PROM(s) containing the configuration data.
Master Parallel (Up or Down) modes generate the CCLK
signal and PROM addresses and receive byte parallel
data.
The data is internally serialized into the FPGA
data-frame format. The up and down selection generates
starting addresses at either zero or 3FFFF, for compatibility
with different microprocessor addressing conventions. The
Unrestricted User-Programmable I/O Pins
I/O
Weak
Pull-up
I/O
These pins can be configured to be input and/or output after configuration is completed.
Before configuration is completed, these pins have an internal high-value pull-up resis-
tor (20 k
- 100 k) that defines the logic level as High.
Table 9: Pin Descriptions (Continued)
Pin Name
I/O
During
Config.
I/O
After
Config.
Pin Description
Table 10: Configuration Modes
Mode
M2
M1
M0
CCLK
Data
Master Serial
0
output
Bit-Serial
Slave Serial
1
input
Bit-Serial
Master
Parallel Up
1
0
output
Byte-Wide,
increment
from 00000
Master
Parallel Down
1
0
output
Byte-Wide,
decrement
from 3FFFF
Peripheral
Synchronous*
0
1
input
Byte-Wide
Peripheral
Asynchronous
1
0
1
output
Byte-Wide
Express
0
1
0
input
Byte-Wide
Reserved
001
——
Product Obsolete or Under Obsolescence
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XC5210-6PQ208C0167 | 制造商:Xilinx 功能描述: |
| XC5210-6PQ208I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC5210-6PQ240C | 功能描述:IC FPGA 324 CLB'S 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:XC5200 產品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數:100 邏輯元件/單元數:238 RAM 位總計:3200 輸入/輸出數:80 門數:3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
| XC5210-6PQ240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC5210-6PQG208C | 制造商:Xilinx 功能描述: |
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