參數(shù)資料
型號(hào)： XC5210-6PQ240I
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（FPGA）
文件頁(yè)數(shù)： 32/73頁(yè)
文件大小： 598K
代理商： XC5210-6PQ240I
R
XC5200 Series Field Programmable Gate Arrays
7-114
November 5, 1998 (Version 5.2)
Configuration Timing
The seven configuration modes are discussed in detail in
this section. Timing specifications are included.
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial configuration bitstream must
be available at the DIN input of the lead FPGA a short
setup time before each rising CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin.
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the sub-
sequent rising CCLK edge.
Figure 28
shows a full master/slave system. An
XC5200-Series device in Slave Serial mode should be con-
nected as shown in the third device from the left.
Slave Serial mode is selected by a <111> on the mode pins
(M2, M1, M0). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resis-
tors during configuration.
Note:
Figure 29: Slave Serial Mode Programming Switching Characteristics
Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
XC5200
MASTER
SERIAL
Spartan,
XC4000E/EX,
XC5200
SLAVE
XC3100A
SLAVE
XC1700E
PROGRAM
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
NOTE:
M2, M1, M0 can be shorted
to VCC if not used as I/O
M2
M0 M1
DOUT
CCLK
DIN
LDC
INIT
CLK
DATA
CE
RESET/OE
VCC
+5 V
CEO
VPP
DONE
INIT
DONE
PROGRAM
PROGRAM
D/P
INIT
RESET
CCLK
DIN
CCLK
DIN
DOUT
DOUT
M2
M0 M1
M1
PWRDN
M0
M2
(Low Reset Option Used)
4.7 K
3.3 K
3.3 K
3.3 K
3.3 K
3.3 K
3.3 K
VCC
X9003_01
N/C
N/C
Figure 28: Master/Slave Serial Mode Circuit Diagram
4 T
CCH
Bit n
Bit n + 1
Bit n
Bit n - 1
3 T
CCO
5 T
CCL
2 T
CCD
1 T
DCC
DIN
CCLK
DOUT
(Output)
X5379
Description
Symbol
Min
20
0
Max
Units
ns
ns
ns
ns
ns
MHz
CCLK
DIN setup
DIN hold
DIN to DOUT
High time
Low time
Frequency
1
2
3
4
5
T
DCC
T
CCD
T
CCO
T
CCH
T
CCL
F
CC
30
45
45
10
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