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參數(shù)資料
| 型號： | XC5210-6PQ240I |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場可編程門陣列（FPGA） |
| 文件頁數(shù)： | 40/73頁 |
| 文件大?。?/td> | 598K |
| 代理商： | XC5210-6PQ240I |
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R
XC5200 Series Field Programmable Gate Arrays
7-122
November 5, 1998 (Version 5.2)
Express Mode
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the con-
figuration data shift registers. A CCLK frequency of 10
MHz is equivalent to an 80 MHz serial rate, because eight
bits of configuration data are loaded per CCLK cycle.
Express mode does not support CRC error checking, but
does support constant-field error checking.
In Express mode, an external signal drives the CCLK input
of the FPGA device. The first byte of parallel configuration
data must be available at the D inputs of the FPGA a short
setup time before the second rising CCLK edge. Subse-
quent data bytes are clocked in on each consecutive rising
CCLK edge.
If the first device is configured in Express mode, additional
devices may be daisy-chained only if every device in the
chain is also configured in Express mode. CCLK pins are
tied together and D0-D7 pins are tied together for all
devices along the chain. A status signal is passed from
DOUT to CS1 of successive devices along the chain. The
lead device in the chain has its CS1 input tied High (or float-
ing, since there is an internal pullup). Frame data is
accepted only when CS1 is High and the device’s configu-
ration memory is not already full. The status pin DOUT is
pulled Low two internal-oscillator cycles after INIT is recog-
nized as High, and remains Low until the device’s configu-
ration memory is full. DOUT is then pulled High to signal
the next device in the chain to accept the configuration data
on the D0-D7 bus.
The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a
large number of devices are included in the chain, deacti-
vate some of the internal pull-ups, since the Low-driving
DONE pin of the last device in the chain must sink the cur-
rent from all pull-ups in the chain. The DONE pull-up is
activated by default. It can be deactivated using an option
in the bitstream generation software.
XC5200 devices in Express mode are always synchronized
to DONE. The device becomes active after DONE goes
High. DONE is an open-drain output. With the DONE pins
tied together, therefore, the external DONE signal stays low
until all devices are configured, then all devices in the daisy
chain become active simultaneously. If the DONE pin of a
device is left unconnected, the device becomes active as
soon as that device has been configured.
Express mode is selected by a <010> on the mode pins
(M2, M1, M0).
INIT
CCLK
CCLK
XC5200
M0
M1
M2
CS1
D0-D7
DATA BUS
PROGRAM
INIT
CCLK
PROGRAM
INIT
DOUT
DONE
DONE
DOUT
To Additional
Optional
Daisy-Chained
Devices
To Additional
Optional
Daisy-Chained
Devices
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
Optional
Daisy-Chained
XC5200
M0
M1
VCC
VCC
4.7K
3.3 k
M2
CS1
D0-D7
PROGRAM
X6611_01
8
8
8
Figure 37: Express Mode Circuit Diagram
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC5210-6PQG208C | 制造商:Xilinx 功能描述: |
| XC52106T144C | 制造商:Xilinx 功能描述: |
| XC5210-6TQ144C | 功能描述:IC FPGA 324 CLB'S 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC5200 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
| XC5210-6TQ144I | 制造商:Xilinx 功能描述: |
| XC5210-6TQ176C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
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