參數(shù)資料
型號: XC5210-6PQ240I
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場可編程門陣列(FPGA)
文件頁數(shù): 34/73頁
文件大?。?/td> 598K
代理商: XC5210-6PQ240I
R
XC5200 Series Field Programmable Gate Arrays
7-116
November 5, 1998 (Version 5.2)
M0
M1
DOUT
VCC
M2
PROGRAM
D7
D6
D5
D4
D3
D2
D1
D0
PROGRAM
CCLK
DIN
M0
M1
M2
DOUT
PROGRAM
EPROM
(8K x 8)
(OR LARGER)
A10
A11
A12
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
DONE
D6
D5
D4
D3
D2
D1
D0
N/C
N/C
CE
OE
XC5200/
XC4000E/EX/
Spartan
SLAVE
8
DATA BUS
CCLK
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
INIT
INIT
. . .
. . .
. . .
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT BETWEEN
ALTERNATIVE CONFIGURATIONS
DONE
TO DIN OF OPTIONAL
DAISY-CHAINED FPGAS
A16
. . .
A17
. . .
HIGH
or
LOW
X9004_01
TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS
3.3 K
4.7K
NOTE:M0 can be shorted
to Ground if not used
as I/O.
XC5200
Master
Parallel
Figure 31: Master Parallel Mode Circuit Diagram
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相關代理商/技術參數(shù)
參數(shù)描述
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