參數(shù)資料
型號: XC6SLX75T-3FG484I
廠商: Xilinx Inc
文件頁數(shù): 52/89頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 6 484FGGBGA
標準包裝: 60
系列: Spartan® 6 LXT
LAB/CLB數(shù): 5831
邏輯元件/單元數(shù): 74637
RAM 位總計: 3170304
輸入/輸出數(shù): 268
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BBGA
供應(yīng)商設(shè)備封裝: 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
56
Clock Buffers and Networks
PLL Switching Characteristics
Table 48: Global Clock Switching Characteristics (BUFGMUX)
Symbol
Description
Devices
Speed Grade
Units
-3
-3N
-2
-1L
TGSI
S pin Setup to I0/I1 inputs
LX devices
0.25
0.31
0.48
ns
LXT devices
0.25
0.31
0.48
N/A
ns
TGIO
BUFGMUX delay from I0/I1 to O
LX devices
0.21
ns
LXT devices
0.21
N/A
ns
Maximum Frequency
FMAX
Global clock tree (BUFGMUX)
LX devices
400
375
250
MHz
LXT devices
400
375
N/A
MHz
Table 49: Input/Output Clock Switching Characteristics (BUFIO2)
Symbol
Description
Devices
Speed Grade
Units
-3
-3N
-2
-1L
TBUFCKO_O
Clock to out delay from I to O
LX devices
0.67
0.82
1.09
1.50
ns
LXT devices
0.67
0.82
1.09
N/A
ns
Maximum Frequency
FMAX
I/O clock tree (BUFIO2)
LX devices
540
525
500
300
MHz
LXT devices
540
525
500
N/A
MHz
Table 50: Input/Output Clock Switching Characteristics (BUFIO2FB)
Symbol
Description
Devices
Speed Grade
Units
-3
-3N
-2
-1L
Maximum Frequency
FMAX
I/O clock tree (BUFIO2FB)
LX devices
1080
1050
950
500
MHz
LXT devices
1080
1050
950
N/A
MHz
Table 51: Input/Output Clock Switching Characteristics (BUFPLL)
Symbol
Description
Devices
Speed Grade
Units
-3
-3N
-2
-1L
Maximum Frequency
FMAX
BUFPLL clock tree (BUFPLL)
LX devices
1080
1050
950
500
MHz
LXT devices
1080
1050
950
N/A
MHz
Table 52: PLL Specification
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
FINMAX
Maximum Input Clock Frequency from I/O Clock
LX devices
540
525
450
300
MHz
LXT devices
540
525
450
N/A
MHz
Maximum Input Clock Frequency from Global Clock
LX devices
400
375
250
MHz
LXT devices
400
375
N/A
MHz
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