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    參數(shù)資料
    

    


    


    
型號：
XC6SLX75T-3FG484I

    

    
廠商：
Xilinx Inc

    

    
文件頁數(shù)：
85/89頁

    

    
文件大?。?/td>
0K

    

    
描述：
IC FPGA SPARTAN 6 484FGGBGA

    

    
標(biāo)準(zhǔn)包裝：
60

    

    
系列：
Spartan® 6 LXT

    

    
LAB/CLB數(shù)：
5831
    		

    

    
邏輯元件/單元數(shù)：
74637
    		

    

    
RAM 位總計(jì)：
3170304
    		

    

    
輸入/輸出數(shù)：
268
    		

    

    
電源電壓：
1.14 V ~ 1.26 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
-40°C ~ 100°C
    		

    

    
封裝/外殼：
484-BBGA
    		

    

    
供應(yīng)商設(shè)備封裝：
484-FBGA
    		

    

    

    

	
    
    
    

    
    
	
    Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
    DS162 (v3.0) October 17, 2011
    Product Specification
    86
    06/14/10
    1.5
    In Table 2, added note 5 and added temperature range to VFS and RFUSE. Removed speed grade
    delineation, revised IRPD description, and updated note 2 in Table 4. Added note 2 to Table 7. Added
    DIFF_MOBILE_DDR to Table 8 and Table 10. Added note 4 to Table 15. Changed minimum DVPPIN in
    Table 16. Updated FGTPDRPCLK in Table 19. Increased maximum TLLSKEW in Table 22. Updated
    descriptions and added data to Table 23. Removed note 1 and added new data to the Networking
    Applications section in Table 25. Updated Table 26 and Table 27 to the data in ISE v12.1 software with
    speed specification v1.08. In Table 28, added DIFF_MOBILE_DDR and updated -4 speed grade data.
    Updated the maximum I/O pairs per bank in Table 33. Updated note 2 on Table 39. Revised the FMAX
    in Table 44. In Table 47, updated description for TSMCKCSO, revised values for TPOR and added Min
    value, added TBPIICCK and TSPIICCK. Also in Table 47, added device dependencies to FSMCCK and
    FRBCCK. Updated and added data to Table 63 through Table 78, and Table 81. In Table 79, added data
    on the XC6SLX45-FG(G)676 and revised the XC6SLX45T and XC6SLX150T values.
    The following changes to this specification are addressed in the product change notice
    XCN10024, MCB Performance and JTAG Revision Code for Spartan-6 LX16 and LX45 FPGAs.
    In Table 2, revised the VCCINT to add the memory controller block extended performance
    specifications. In Table 25, changed the standard specifications and added extended performance
    specifications for the memory controller block and note 2. Added note 4 and updated values in
    06/24/10
    1.6
    Production release of XC6SLX45T (-2 and -3 speed grades), XC6SLX16 and XC6SLX45 (-3 speed
    grade) devices which includes changes to Table 26 and Table 27 (ISE v12.1 software with speed
    specification v1.08).
    Added the -3N speed grade, which designates Spartan-6 devices that do not support MCB
    functionality. This includes changes to Table 2 (note 2), Table 25 (note 4), and Switching
    Updated Simultaneously Switching Outputs discussion. Added -3 speed grade values for TTAP and
    FMINCAL values in Table 39. In Table 40, updated TRPW (-2 and -3 speed grade) values and FTOG (-3
    speed grade) values. In Table 48, updated TGIO (-2 and -3 speed grade) values. Updated -3 values in
    spread spectrum section of Table 57.
    07/16/10
    1.7
    Production release of specific devices listed in Table 26 and Table 27 using ISE v12.2 software with
    speed specification v1.11. Added note 4 advising designers of the patch which contains v1.11. Also
    updated the -1L speed specification to v1.04. Updated numerous -4 and -1L values. Added -4 TTAP
    values and FMINCAL to Table 39. Revised TCINCK/TCKCIN in Table 40. In Table 41, revised TSHCKO. In
    Table 42, revised TREG. Added new -1L values to Table 47. Added and updated values in Table 79.
    07/26/10
    1.8
    Production release of XC6SLX25, XC6SLX25T, XC6SLX100 and XC6SLX100T in the specific speed
    grades listed in Table 26 and Table 27 using ISE v12.2 software with speed specification v1.11. Added
    note 7 to Table 2 and moved VFS and RFUSE to a new Table 3. Added IHS and note 4 to Table 4. Added
    note 1 to Table 28. Added and updated SSO limits per VCCO/GND pairs in Table 34. Added note 3 to
    Table 47. In Table 54, removed -1L specifications for CLKOUT_PER_JITT_DV1/2 and revised
    CLKIN_CLKFB_PHASE and CLKOUT_PHASE_DLL values. Updated note 3 in both Table 56 and
    08/23/10
    1.9
    Updated values for FGTPRANGE1, FGTPRANGE2, and FGPLLMIN in Table 18. Revised -3 and -4 values in
    Table 21. Removed the -1L speed grade readback support restriction and note 3 in Table 47.
    11/05/10
    1.10
    Production release of XC6SLX4 and XC6SLX9 in the specific speed grades listed in Table 26 and
    Table 27 using ISE v12.3 software with speed specification v1.12 for the -2 speed grade available in
    the 12.3 Speed Files Patch. Added note 3 advising designers of the patch which contains v1.12.
    In Table 2, added note 4. In Table 4, added note 2. In Table 10, added notes 2 and 3. In Table 44, added
    note 2. In Table 47, updated symbol for TSMWCCK/TSMCCKW , changed -1L values for TUSERCCLKH and
    TUSERCCLKL , and added and revised the modes for FMCCK and FSMCCK. In Table 53, redefined and
    expanded description for CLKIN_FREQ_DLL and rewrote note 3. Updated title of Table 58. Also in
    Table 78, revised TDCD_CLK for XC6SLX150 and XC6SLX150T. Changed description of TPSFD/ TPHFD
    For the -1L speed grade, updated data sheet to ISE 12.3 software with speed specification v1.05 which
    revised the values in the following tables: Table 25, Table 28, Table 35, Table 36, Table 37, Table 40
    Date
    Version
    Description of Revisions
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
XC6SLX75T-3FG676C
 制造商:Xilinx 功能描述:IC FPGA SPARTAN 6 75K 676BGA 制造商:Xilinx 功能描述:IC FPGA 348 I/O 676FCBGA

    

    
XC6SLX75T-3FG676I
功能描述:IC FPGA SPARTAN 6 676FGGBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5

    

    
XC6SLX75T-3FGG484C
功能描述:IC FPGA SPARTAN 6 74K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5

    

    
XC6SLX75T-3FGG484I
功能描述:IC FPGA SPARTAN 6 74K 484FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5

    

    
XC6SLX75T-3FGG676C
功能描述:IC FPGA SPARTAN 6 74K 676FGGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 6 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5

    

    
    
    
    
	
    	
    
    
     
     
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