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| 型號： | XCF32PVOG48C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 1/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SRL 1.8V 32M GATE 48TSOP |
| 產(chǎn)品變化通告： | VOG48 New Shipping Trays Notification 25/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 存儲容量： | 32Mb |
| 電源電壓： | 1.65 V ~ 2 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-TFSOP（0.724"，18.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 601 (CN2011-ZH PDF) |
| 其它名稱： | 122-1458 122-1458-5 122-1458-5-ND |
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DS123 (v2.18) May 19, 2010
Product Specification
1
Copyright 2003–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
Features
In-System Programmable PROMs for Configuration of
Xilinx FPGAs
Low-Power Advanced CMOS NOR Flash Process
Endurance of 20,000 Program/Erase Cycles
Operation over Full Industrial Temperature Range
(–40°C to +85°C)
IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)
Support for Programming, Prototyping, and Testing
JTAG Command Initiation of Standard FPGA
Configuration
Cascadable for Storing Longer or Multiple Bitstreams
Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)
I/O Pins Compatible with Voltage Levels Ranging From
1.8V to 3.3V
Design Support Using the Xilinx ISE Alliance and
Foundation Software Packages
XCF01S/XCF02S/XCF04S
3.3V Supply Voltage
Serial FPGA Configuration Interface
Available in Small-Footprint VO20 and VOG20
Packages
XCF08P/XCF16P/XCF32P
1.8V Supply Voltage
Serial or Parallel FPGA Configuration Interface
Available in Small-Footprint VOG48, FS48, and
FSG48 Packages
Design Revision Technology Enables Storing and
Accessing Multiple Design Revisions for
Configuration
Built-In Data Decompressor Compatible with Xilinx
Advanced Compression Technology
Description
Xilinx introduces the Platform Flash series of in-system
programmable configuration PROMs. Available in
1 to 32 Mb densities, these PROMs provide an easy-to-use,
cost-effective, and reprogrammable method for storing large
Xilinx FPGA configuration bitstreams. The Platform Flash
PROM series includes both the 3.3V XCFxxS PROM and
the 1.8V XCFxxP PROM. The XCFxxS version includes
4 Mb, 2 Mb, and 1 Mb PROMs that support Master Serial
and Slave Serial FPGA configuration modes (Figure 1,
page 2). The XCFxxP version includes 32 Mb, 16 Mb, and
8 Mb PROMs that support Master Serial, Slave Serial,
Master SelectMAP, and Slave SelectMAP FPGA
configuration modes (Figure 2, page 2).
When driven from a stable, external clock, the PROMs can
output data at rates up to 33 MHz. Refer to "AC Electrical
Characteristics," page 16 for timing considerations.
A summary of the Platform Flash PROM family members
and supported features is shown in Table 1.
35
Platform Flash In-System Programmable
Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
R
Table 1: Platform Flash PROM Features
Device
Density
(Mb)
VCCINT
(V)
VCCO Range
(V)
VCCJ Range
(V)
Packages
Program In-system
via JTAG
Serial
Config.
Parallel
Config.
Design
Revisioning
Compression
XCF01S
1
3.3
1.8 – 3.3
2.5 – 3.3
VO20/VOG20
XCF02S
2
3.3
1.8 – 3.3
2.5 – 3.3
VO20/VOG20
XCF04S
4
3.3
1.8 – 3.3
2.5 – 3.3
VO20/VOG20
XCF08P
8
1.8
1.8 – 3.3
2.5 – 3.3
VO48/VOG48
FS48/FSG48
(1)
XCF16P
16
1.8
1.8 – 3.3
2.5 – 3.3
VO48/VOG48
FS48/FSG48
XCF32P
32
1.8
1.8 – 3.3
2.5 – 3.3
VO48/VOG48
FS48/FSG48
Notes:
1.
XCF08P supports storage of a design revision only when cascaded with another XCFxxP PROM. See "Design Revisioning," page 8 for details.
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