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參數資料
| 型號： | XCF32PVOG48C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 15/35頁 |
| 文件大小： | 0K |
| 描述： | IC PROM SRL 1.8V 32M GATE 48TSOP |
| 產品變化通告： | VOG48 New Shipping Trays Notification 25/Apr/2011 |
| 標準包裝： | 96 |
| 可編程類型： | 系統(tǒng)內可編程 |
| 存儲容量： | 32Mb |
| 電源電壓： | 1.65 V ~ 2 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-TFSOP（0.724"，18.40mm 寬） |
| 供應商設備封裝： | 48-TSOP |
| 包裝： | 管件 |
| 產品目錄頁面： | 601 (CN2011-ZH PDF) |
| 其它名稱： | 122-1458 122-1458-5 122-1458-5-ND |
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Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
22
R
TSB
BUSY setup time to CLKOUT when VCCO = 3.3V or 2.5V
12
–
ns
BUSY setup time to CLKOUT when VCCO = 1.8V
12
–
ns
THB
BUSY hold time to CLKOUT when VCCO = 3.3V or 2.5V
8
–
ns
BUSY hold time to CLKOUT when VCCO = 1.8V
8
–
ns
TCEC
CE to CLKOUT delay(7) when VCCO = 3.3V or 2.5V
0
1
s
CE to CLKOUT delay(7) when VCCO = 1.8V
0
1
s
TOEC
OE/RESET to CLKOUT delay(7) when VCCO = 3.3V or 2.5V
0
1
s
OE/RESET to CLKOUT delay(7) when VCCO = 1.8V
0
1
s
TCFC
CF to CLKOUT delay(7) when VCCO = 3.3V or 2.5V
0
–
CF to CLKOUT delay(7) when VCCO = 1.8V
0
–
TCDD
CLKOUT to data delay when VCCO = 3.3V or 2.5V(8)
–30
ns
CLKOUT to data delay when VCCO = 1.8V(8)
–30
ns
TDDC
Data setup time to CLKOUT
when VCCO = 3.3V or 2.5V with decompression(8)(11)
5ns
Data setup time to CLKOUT when VCCO = 1.8V with decompression(8)(11)
5ns
TCOH
Data hold from CLKOUT when VCCO = 3.3V or 2.5V
3
–
ns
Data hold from CLKOUT when VCCO = 1.8V
3
–
ns
Data hold from CLKOUT when VCCO = 3.3V or 2.5V with decompression(11)
3–
ns
Data hold from CLKOUT when VCCO = 1.8V with decompression(11)
3–
ns
TSXT
EN_EXT_SEL setup time to CF, CE, or OE/RESET when VCCO = 3.3V or 2.5V
300
–
ns
EN_EXT_SEL setup time to CF, CE, or OE/RESET when VCCO = 1.8V
300
–
ns
THXT
EN_EXT_SEL hold time from CF, CE, or OE/RESET when VCCO = 3.3V or 2.5V
300
–
ns
EN_EXT_SEL hold time from CF, CE, or OE/RESET when VCCO = 1.8V
300
–
ns
TSRV
REV_SEL setup time to CF, CE, or OE/RESET when VCCO = 3.3V or 2.5V
300
–
ns
REV_SEL setup time to CF, CE, or OE/RESET when VCCO = 1.8V
300
–
ns
THRV
REV_SEL hold time from CF, CE, or OE/RESET when VCCO = 3.3V or 2.5V
300
–
ns
REV_SEL hold time from CF, CE, or OE/RESET when VCCO = 1.8V
300
–
ns
FF
CLKOUT default (fast) frequency(9)
25
50
MHz
CLKOUT default (fast) frequency with decompression(11)
12.5
25
MHz
FS
CLKOUT alternate (slower) frequency(10)
12.5
25
MHz
CLKOUT alternate (slower) frequency with decompression(11)
6
12.5
MHz
Notes:
1.
AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P.
2.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady-state active levels.
3.
Guaranteed by design, not tested.
4.
All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5.
If THCE High < 2 s, TCE = 2 s.
6.
If THOE Low < 2 s, TOE = 2 s.
7.
The delay before the enabled CLKOUT signal begins clocking data out of the device is dependent on the clocking configuration. The delay
before CLKOUT is enabled increases if decompression is enabled.
8.
Slower CLK frequency option might be required to meet the FPGA data sheet setup time.
9.
Typical CLKOUT default (fast) period = 25 ns (40 MHz).
10. Typical CLKOUT alternate (slower) period = 50 ns (20 MHz).
11. When decompression is enabled, the CLKOUT signal becomes a controlled clock output. When decompressed data is available, CLKOUT
toggles at the source clock frequency (either the selected internal clock frequency or the external CLK input frequency). When
decompressed data is not available, the CLKOUT pin is parked High. If CLKOUT is used, then it must be pulled High externally using a
4.7 k
Ω pull-up to V
CCO.
12. When JTAG CONFIG command is issued, PROM drives CF Low for at least the THCF minimum.
Symbol
Description
XCF08P, XCF16P,
XCF32P
Units
Min
Max
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