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參數(shù)資料
| 型號(hào)： | XCV200-6PQG240I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 167K |
| 代理商： | XCV200-6PQG240I |
Virtex 2.5 V Field Programmable Gate Arrays
R
Module 3 of 4
DS003-3 (v3.2) September 10, 2002
22
1-800-255-7778
Production Product Specification
Revision History
Figure 1: Frequency Tolerance and Clock Jitter
Date
Version
Revision
11/98
1.0
Initial Xilinx release.
01/99
1.2
Updated package drawings and specs.
02/99
1.3
Update of package drawings, updated specifications.
05/99
1.4
Addition of package drawings and specifications.
05/99
1.5
Replaced FG 676 & FG680 package drawings.
07/99
1.6
Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit
Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O
Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and
new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and
Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19.
Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated
IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate.
Added IOB Input Switching Characteristics Standard Adjustments.
09/99
1.7
Speed grade update to preliminary status, Power-on specification and Clock-to-Out
Minimums additions, "0" hold time listing explanation, quiescent current listing update, and
Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE.
01/00
1.8
Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479,
117153, 117154, and 117612. Modified notes for Recommended Operating Conditions
(voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43.
TCLKIN
TCLKIN + TIPTOL
Period Tolerance: the allowed input clock period change in nanoseconds.
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
_
ds003_20c_110399
Ideal Period
Actual Period
+
Jitter
+/- Jitter
+ Maximum
Phase Difference
Phase Offset and Maximum Phase Difference
+ Phase Offset
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV200E | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XCV200E-6BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV200E-6BG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV200E-6BG352C | 功能描述:IC FPGA 1.8V C-TEMP 352-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV200E-6BG352C0773 | 制造商:Xilinx 功能描述: |
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