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參數(shù)資料
| 型號： | XCV200-6PQG240I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 167K |
| 代理商： | XCV200-6PQG240I |
Virtex 2.5 V Field Programmable Gate Arrays
R
DS003-3 (v3.2) September 10, 2002
Module 3 of 4
Production Product Specification
1-800-255-7778
5
Virtex Switching Characteristics
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation net list. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Virtex devices unless
otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in , page 6.
Description
Device
Symbol
Speed Grade
Units
Min
-6
-5
-4
Propagation Delays
Pad to I output, no delay
All
TIOPI
0.39
0.8
0.9
1.0
ns, max
Pad to I output, with delay
XCV50
TIOPID
0.8
1.5
1.7
1.9
ns, max
XCV100
0.8
1.5
1.7
1.9
ns, max
XCV150
0.8
1.5
1.7
1.9
ns, max
XCV200
0.8
1.5
1.7
1.9
ns, max
XCV300
0.8
1.5
1.7
1.9
ns, max
XCV400
0.9
1.8
2.0
2.3
ns, max
XCV600
0.9
1.8
2.0
2.3
ns, max
XCV800
1.1
2.1
2.4
2.7
ns, max
XCV1000
1.1
2.1
2.4
2.7
ns, max
Pad to output IQ via transparent
latch, no delay
All
TIOPLI
0.8
1.6
1.8
2.0
ns, max
Pad to output IQ via transparent
latch, with delay
XCV50
TIOPLID
1.9
3.7
4.2
4.8
ns, max
XCV100
1.9
3.7
4.2
4.8
ns, max
XCV150
2.0
3.9
4.3
4.9
ns, max
XCV200
2.0
4.0
4.4
5.1
ns, max
XCV300
2.0
4.0
4.4
5.1
ns, max
XCV400
2.1
4.1
4.6
5.3
ns, max
XCV600
2.1
4.2
4.7
5.4
ns, max
XCV800
2.2
4.4
4.9
5.6
ns, max
XCV1000
2.3
4.5
5.1
5.8
ns, max
Sequential Delays
Clock CLK
All
Minimum Pulse Width, High
TCH
0.8
1.5
1.7
2.0
ns, min
Minimum Pulse Width, Low
TCL
0.8
1.5
1.7
2.0
ns, min
Clock CLK to output IQ
TIOCKIQ
0.2
0.7
0.8
ns, max
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|---|---|
| XCV200E | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
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| XCV200E-6BG352C | 功能描述:IC FPGA 1.8V C-TEMP 352-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV200E-6BG352C0773 | 制造商:Xilinx 功能描述: |
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