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參數(shù)資料
| 型號(hào)： | XCV200-6PQG240I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 167K |
| 代理商： | XCV200-6PQG240I |
Virtex 2.5 V Field Programmable Gate Arrays
R
Module 3 of 4
DS003-3 (v3.2) September 10, 2002
8
1-800-255-7778
Production Product Specification
Clock CLK to Pad delay with OBUFT
enabled (non-3-state)
TIOCKP
1.0
2.9
3.2
3.5
ns, max
Clock CLK to Pad high-impedance
(synchronous)(1)
TIOCKHZ
1.1
2.3
2.5
2.9
ns, max
Clock CLK to valid data on Pad delay, plus
enable delay for OBUFT
TIOCKON
1.5
3.4
3.7
4.1
ns, max
Setup and Hold Times before/after Clock CLK(2)
Setup Time / Hold Time
O input
TIOOCK/TIOCKO
0.51 / 0
1.1 / 0
1.2 / 0
1.3 / 0
ns, min
OCE input
TIOOCECK/TIOCKOCE
0.37 / 0
0.8 / 0
0.9 / 0
1.0 / 0
ns, min
SR input (OFF)
TIOSRCKO/TIOCKOSR
0.52 / 0
1.1 / 0
1.2 / 0
1.4 / 0
ns, min
3-State Setup Times, T input
TIOTCK/TIOCKT
0.34 / 0
0.7 / 0
0.8 / 0
0.9 / 0
ns, min
3-State Setup Times, TCE input
TIOTCECK/TIOCKTCE
0.41 / 0
0.9 / 0
1.1 / 0
ns, min
3-State Setup Times, SR input (TFF)
TIOSRCKT/TIOCKTSR
0.49 / 0
1.0 / 0
1.1 / 0
1.3 / 0
ns, min
Set/Reset Delays
SR input to Pad (asynchronous)
TIOSRP
1.6
3.8
4.1
4.6
ns, max
SR input to Pad high-impedance
(asynchronous)(1)
TIOSRHZ
1.6
3.1
3.4
3.9
ns, max
SR input to valid data on Pad
(asynchronous)
TIOSRON
2.0
4.2
4.6
5.1
ns, max
GSR to Pad
TIOGSRQ
4.9
9.7
10.9
12.5
ns, max
Notes:
1.
3-state turn-off delays should not be adjusted.
2.
A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
Description
Symbol
Speed Grade
Units
Min
-6-5-4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV200E | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XCV200E-6BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV200E-6BG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV200E-6BG352C | 功能描述:IC FPGA 1.8V C-TEMP 352-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV200E-6BG352C0773 | 制造商:Xilinx 功能描述: |
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