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| 型號(hào)： | XCV200-6PQG240I |
| 廠商： | XILINX INC |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PQFP240 |
| 封裝： | PLASTIC, QFP-240 |
| 文件頁(yè)數(shù)： | 22/24頁(yè) |
| 文件大?。?/td> | 167K |
| 代理商： | XCV200-6PQG240I |
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Virtex 2.5 V Field Programmable Gate Arrays
R
DS003-3 (v3.2) September 10, 2002
Module 3 of 4
Production Product Specification
1-800-255-7778
7
IOB Input Switching Characteristics Standard Adjustments
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 9.
Description
Symbol
Standard(1)
Speed Grade
Units
Min
-6-5-4
Data Input Delay Adjustments
Standard-specific data input delay
adjustments
TILVTTL
LVTTL
0
ns
TILVCMOS2
LVCMOS2
–0.02
–0.04
–0.05
ns
TIPCI33_3
PCI, 33 MHz, 3.3 V
–0.05
–0.11
–0.12
–0.14
ns
TIPCI33_5
PCI, 33 MHz, 5.0 V
0.13
0.25
0.28
0.33
ns
TIPCI66_3
PCI, 66 MHz, 3.3 V
–0.05
–0.11
–0.12
–0.14
ns
TIGTL
GTL
0.100.200.230.26
ns
TIGTLP
GTL+
0.06
0.11
0.12
0.14
ns
TIHSTL
HSTL
0.02
0.03
0.04
ns
TISSTL2
SSTL2
–0.04
–0.08
–0.09
–0.10
ns
TISSTL3
SSTL3
–0.02
–0.04
–0.05
–0.06
ns
TICTT
CTT
0.010.020.020.02
ns
TIAGP
AGP
–0.03
–0.06
–0.07
–0.08
ns
Notes:
1.
Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
Description
Symbol
Speed Grade
Units
Min
-6-5-4
Propagation Delays
O input to Pad
TIOOP
1.2
2.9
3.2
3.5
ns, max
O input to Pad via transparent latch
TIOOLP
1.4
3.4
3.7
4.0
ns, max
3-State Delays
T input to Pad high-impedance(1)
TIOTHZ
1.0
2.0
2.2
2.4
ns, max
T input to valid data on Pad
TIOTON
1.4
3.1
3.3
3.7
ns, max
T input to Pad high-impedance via
transparent latch(1)
TIOTLPHZ
1.2
2.4
2.6
3.0
ns, max
T input to valid data on Pad via
transparent latch
TIOTLPON
1.6
3.5
3.8
4.2
ns, max
GTS to Pad high impedance(1)
TGTS
2.5
4.9
5.5
6.3
ns, max
Sequential Delays
Clock CLK
Minimum Pulse Width, High
TCH
0.8
1.5
1.7
2.0
ns, min
Minimum Pulse Width, Low
TCL
0.8
1.5
1.7
2.0
ns, min
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|---|---|
| XCV200E | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Field Programmable Gate Arrays |
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