參數(shù)資料
型號(hào)： XCV405E-6BG560C
廠商： Xilinx Inc
文件頁數(shù)： 17/118頁
文件大?。?/td> 0K
描述： IC FPGA 1.8V C-TEMP 560-MBGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-E EM
LAB/CLB數(shù)： 2400
邏輯元件/單元數(shù)： 10800
RAM 位總計(jì)： 573440
輸入/輸出數(shù)： 404
門數(shù)： 129600
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 560-LBGA，金屬
供應(yīng)商設(shè)備封裝： 560-MBGA（42.5x42.5）
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-4 (v3.0) March 21, 2014
Module 4 of 4
37
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
FG900 Differential Pin Pairs
Virtex-E Extended Memory devices have differential pin
pairs that can also provide other functions when not used as
a differential pair. A
√ in the AO column indicates that the pin
pair can be used as an asynchronous output for all devices
provided in this package.
Pairs with a note number in the AO column are device
dependent. They can have asynchronous outputs if the pin
pair is in the same CLB row and column in the device. Num-
bers in this column refer to footnotes that indicate which
devices have pin pairs that can be asynchronous outputs.
The Other Functions column indicates alternative func-
tion(s) not available when the pair is used as a differential
pair or differential clock.
NA
GND
AC8
NA
GND
H8
NA
GND
AD7
NA
GND
B8
NA
GND
AE6
NA
GND
G7
NA
GND
F6
NA
GND
AF5
NA
GND
E5
NA
GND
AG4
NA
GND
D4
NA
GND
V3
NA
GND
N3
NA
GND
C3
NA
GND
AK2
NA
GND
AH3
NA
GND
AC2
NA
GND
H2
NA
GND
B2
NA
GND
A2
NA
GND
AK1
NA
GND
AJ2
NA
GND
AJ1
NA
GND
A1
NA
GND
B1
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
Table 6:
FG900 Differential Pin Pair Summary —
XCV812E
Pair
Bank
P
Pin
N
Pin
AO
Other
Functions
GCLK LVDS
3
0
C15
A15
NA
IO LVDS 34
2
1
E15
E16
NA
IO LVDS 34
1
5
AK16
AH16
NA
IO LVDS 177
0
4
AJ16
AF16
NA
IO LVDS 177
IO LVDS
Total Pairs: 235, Asynchronous Output Pairs: 85
10
G8
D5
√
-
20
H9
A3
√
-
40
D6
A4
√
-
50
B5
E7
√
VREF
60
F8
A5
-
70
N11
D7
-
80
E8
G9
√
-
90
J11
A6
√
VREF
10
0
B7
C7
-
11
0
H10
C8
-
12
0
F10
G10
√
-
13
0
H11
A8
√
VREF
15
0
J12
B9
-
17
0
B10
G11
-
19
0
F11
H13
√
-
20
0
D11
E11
√
-
22
0
C11
F12
√
-
23
0
D12
A10
√
VREF
24
0
A11
E12
-
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV405E-6BG560I 功能描述:IC FPGA 1.8V 560-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XCV405E-6BG676C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-6BG676I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-6BG900C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-6BG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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