參數(shù)資料
型號： XCV405E-6BG560C
廠商： Xilinx Inc
文件頁數(shù)： 49/118頁
文件大?。?/td> 0K
描述： IC FPGA 1.8V C-TEMP 560-MBGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-E EM
LAB/CLB數(shù)： 2400
邏輯元件/單元數(shù)： 10800
RAM 位總計： 573440
輸入/輸出數(shù)： 404
門數(shù)： 129600
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 560-LBGA，金屬
供應(yīng)商設(shè)備封裝： 560-MBGA（42.5x42.5）
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
32
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Fundamentals
Modern bus applications, pioneered by the largest and most
influential companies in the digital electronics industry, are
commonly introduced with a new I/O standard tailored spe-
cifically to the needs of that application. The bus I/O stan-
dards provide specifications to other vendors who create
products designed to interface with these applications.
Each standard often has its own specifications for current,
voltage, I/O buffering, and termination techniques.
The ability to provide the flexibility and time-to-market
advantages of programmable logic is increasingly depen-
dent on the capability of the programmable logic device to
support an ever increasing variety of I/O standards
The SelectI/O resources feature highly configurable input
and output buffers which provide support for a wide variety
of I/O standards. As shown in Table 18, each buffer type can
support a variety of voltage requirements.
Overview of Supported I/O Standards
This section provides a brief overview of the I/O standards
supported by all Virtex-E devices.
While most I/O standards specify a range of allowed volt-
ages, this document records typical voltage values only.
Detailed information on each specification can be found on
the Electronic Industry Alliance Jedec website at:
LVTTL — Low-Voltage TTL
The Low-Voltage TTL, or LVTTL standard is a general pur-
pose EIA/JESDSA standard for 3.3 V applications that uses
an LVTTL input buffer and a Push-Pull output buffer. This
standard requires a 3.3 V output source voltage (VCCO), but
does not require the use of a reference voltage (VREF) or a
termination voltage (VTT).
LVCMOS2 — Low-Voltage CMOS for 2.5 Volts
The Low-Voltage CMOS for 2.5 Volts or lower, or LVCMOS2
standard is an extension of the LVCMOS standard (JESD
8.-5) used for general purpose 2.5 V applications. This stan-
dard requires a 2.5 V output source voltage (VCCO), but
does not require the use of a reference voltage (VREF) or a
board termination voltage (VTT).
LVCMOS18 — 1.8 V Low Voltage CMOS
This standard is an extension of the LVCMOS standard. It is
used in general purpose 1.8 V applications. The use of a
reference voltage (VREF) or a board termination voltage
(VTT) is not required.
PCI — Peripheral Component Interface
The Peripheral Component Interface, or PCI standard spec-
ifies support for both 33 MHz and 66 MHz PCI bus applica-
tions. It uses a LVTTL input buffer and a Push-Pull output
buffer. This standard does not require the use of a reference
voltage (VREF) or a board termination voltage (VTT), how-
ever, it does require a 3.3 V output source voltage (VCCO).
GTL — Gunning Transceiver Logic Terminated
The Gunning Transceiver Logic, or GTL standard is a
high-speed bus standard (JESD8.3) invented by Xerox.
Xilinx has implemented the terminated variation for this
standard. This standard requires a differential amplifier
input buffer and a Open Drain output buffer.
GTL+ — Gunning Transceiver Logic Plus
The Gunning Transceiver Logic Plus, or GTL+ standard is a
high-speed bus standard (JESD8.3) first used by the Pen-
tium Pro processor.
HSTL — High-Speed Transceiver Logic
The High-Speed Transceiver Logic, or HSTL standard is a
general purpose high-speed, 1.5 V bus standard sponsored
by IBM (EIA/JESD 8-6). This standard has four variations or
classes. SelectI/O devices support Class I, III, and IV. This
Table 18:
Virtex-E Supported I/O Standards
I/O
Standard
Output
VCCO
Input
VCCO
Input
VREF
Board
Termination
Voltage (VTT)
LVTTL
3.3
N/A
LVCMOS2
2.5
N/A
LVCMOS18
1.8
N/A
SSTL3 I & II
3.3
N/A
1.50
SSTL2 I & II
2.5
N/A
1.25
GTL
N/A
0.80
1.20
GTL+
N/A
1.0
1.50
HSTL I
1.5
N/A
0.75
HSTL III & IV
1.5
N/A
0.90
1.50
CTT
3.3
N/A
1.50
AGP-2X
3.3
N/A
1.32
N/A
PCI33_3
3.3
N/A
PCI66_3
3.3
N/A
BLVDS & LVDS
2.5
N/A
LVPECL
3.3
N/A
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV405E-6BG560I 功能描述:IC FPGA 1.8V 560-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XCV405E-6BG676C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-6BG676I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-6BG900C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-6BG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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