參數(shù)資料
型號： XCV405E-6BG560C
廠商： Xilinx Inc
文件頁數(shù)： 67/118頁
文件大小： 0K
描述： IC FPGA 1.8V C-TEMP 560-MBGA
產(chǎn)品變化通告： FPGA Family Discontinuation 18/Apr/2011
標準包裝： 1
系列： Virtex®-E EM
LAB/CLB數(shù)： 2400
邏輯元件/單元數(shù)： 10800
RAM 位總計： 573440
輸入/輸出數(shù)： 404
門數(shù)： 129600
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 560-LBGA，金屬
供應商設備封裝： 560-MBGA（42.5x42.5）
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
48
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Creating LVDS Output Buffers
LVDS output buffer can be placed in wide number of IOB
locations. The exact location are dependent on the package
that is used. The Virtex-E package information lists the pos-
sible locations as IO_L#P for the P-side and IO_L#N for the
N-side where # is the pair number.
HDL Instantiation
Both output buffers are required to be instantiated in the
design and placed on the correct IO_L#P and IO_L#N loca-
tions. The IOB must have the same net source the following
pins, clock (C), set/reset (SR), output (O), output clock
enable (OCE). In addition, the output (O) pins must be
inverted with respect to each other, and if output registers
are used, the INIT states must be opposite values (one
HIGH and one LOW). Failure to follow these rules leads to
DRC errors in software.
VHDL Instantiation
data0_p
: OBUF_LVDS port map
(I=>data_int(0),
O=>data_p(0));
data0_inv: INV
port map
(I=>data_int(0),
O=>data_n_int(0));
data0_n
: OBUF_LVDS port map
(I=>data_n_int(0), O=>data_n(0));
Verilog Instantiation
OBUF_LVDS data0_p
(.I(data_int[0]),
.O(data_p[0]));
INV
data0_inv (.I(data_int[0],
.O(data_n_int[0]);
OBUF_LVDS data0_n
(.I(data_n_int[0]),
.O(data_n[0]));
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the UCF or NCF file.
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous Outputs
If the outputs are synchronous (registered in the IOB), then
any IO_L#P|N pair can be used. If the outputs are asynchro-
nous (no output register), then they must use one of the
pairs that are part of the same IOB group at the end of a
ROW or at the top/bottom of a COLUMN in the device.
The LVDS pairs that can be used as asynchronous outputs
are listed in the Virtex-E pinout tables. Some pairs are
marked as asynchronous-capable for all devices in that
package, and others are marked as available only for that
device in the package. If the device size might change at
some point in the product lifetime, then only the common
pairs for all packages should be used.
Adding an Output Register
All LVDS buffers can have an output register in the IOB. The
output registers must be in both the P-side and N-side IOBs.
All the normal IOB register options are available (FD, FDE,
FDC, FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD,
LDE, LDC, LDCE, LDP, LDPE). The register elements can
be inferred or explicitly instantiated in the HDL code.
Special care must be taken to insure that the D pins of the
registers are inverted and that the INIT states of the regis-
ters are opposite. The clock pin (C), clock enable (CE) and
set/reset (CLR/PRE or S/R) pins must connect to the same
source. Failure to do this leads to a DRC error in the soft-
ware.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b”
is both inputs and outputs.
To improve design coding times VHDL and Verilog synthe-
sis macro libraries have been developed to explicitly create
these structures. The output library macros are listed in
Table 43. The O and OB inputs to the macros are the exter-
nal net connections.
Table 43:
Output Library Macros
Name
Inputs
Outputs
OBUFDS_FD_LVDS
D, C
O, OB
OBUFDS_FDE_LVDS
DD, CE, C
O, OB
OBUFDS_FDC_LVDS
D, C, CLR
O, OB
OBUFDS_FDCE_LVDS
D, CE, C, CLR
O, OB
OBUFDS_FDP_LVDS
D, C, PRE
O, OB
OBUFDS_FDPE_LVDS
D, CE, C, PRE
O, OB
OBUFDS_FDR_LVDS
D, C, R
O, OB
OBUFDS_FDRE_LVDS
D, CE, C, R
O, OB
OBUFDS_FDS_LVDS
D, C, S
O, OB
OBUFDS_FDSE_LVDS
D, CE, C, S
O, OB
OBUFDS_LD_LVDS
D, G
O, OB
OBUFDS_LDE_LVDS
D, GE, G
O, OB
OBUFDS_LDC_LVDS
D, G, CLR
O, OB
OBUFDS_LDCE_LVDS
D, GE, G, CLR
O, OB
OBUFDS_LDP_LVDS
D, G, PRE
O, OB
OBUFDS_LDPE_LVDS
D, GE, G, PRE
O, OB
相關PDF資料
PDF描述
HMC43DRAS CONN EDGECARD 86POS R/A .100 SLD
AMM36DSEN CONN EDGECARD 72POS .156 EYELET
AMM36DSEH CONN EDGECARD 72POS .156 EYELET
AMM36DRTN CONN EDGECARD 72POS DIP .156 SLD
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
XCV405E-6BG560I 功能描述:IC FPGA 1.8V 560-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XCV405E-6BG676C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-6BG676I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-6BG900C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-6BG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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