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參數(shù)資料
| 型號： | XCV405E-6FG676I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| 中文描述： | FPGA, 2400 CLBS, 129600 GATES, 357 MHz, PBGA676 |
| 封裝： | PLASTIC, FBGA-676 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 191K |
| 代理商： | XCV405E-6FG676I |
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 3 of 4
DS025-3 (v2.3.2) March 14, 2003
18
1-800-255-7778
R
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those
parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the
recommended operating conditions.
Description
Symbol
F
CLKIN
Speed Grade
Units
-8
-7
-6
Min
Max
Min
Max
Min
Max
Input Clock Frequency (CLKDLLHF)
FCLKINHF
60
320
60
320
60
260
MHz
Input Clock Frequency (CLKDLL)
FCLKINLF
25
160
25
160
25
135
MHz
Input Clock Low/High Pulse Width
TDLLPW
≥25 MHz
5.0
ns
≥50 MHz
3.0
ns
≥100 MHz
2.4
ns
≥150 MHz
2.0
ns
≥200 MHz
1.8
ns
≥250 MHz
1.5
ns
≥300 MHz
1.3
NA
ns
Figure 4: DLL Timing Waveforms
TCLKIN
TCLKIN + TIPTOL
Period Tolerance: the allowed input clock period change in nanoseconds.
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
_
ds022_24_091200
Ideal Period
Actual Period
+
Jitter
+/- Jitter
+ Maximum
Phase Difference
Phase Offset and Maximum Phase Difference
+ Phase Offset
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV405E-6FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-6FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG404I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG556C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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