參數(shù)資料
型號： XCV405E-6FG676I
廠商： XILINX INC
元件分類： FPGA
英文描述： Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
中文描述： FPGA, 2400 CLBS, 129600 GATES, 357 MHz, PBGA676
封裝： PLASTIC, FBGA-676
文件頁數(shù)： 20/20頁
文件大小： 191K
代理商： XCV405E-6FG676I
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v2.3.2) March 14, 2003
Module 3 of 4
1-800-255-7778
9
R
Calculation of Tioop as a Function of Capacitance
Tioop is the propagation delay from the O Input of the IOB to the
pad. The values for Tioop are based on the standard capacitive
load (Csl) for each I/O standard as listed in Table 2.
For other capacitive loads, use the formulas below to calcu-
late the corresponding Tioop.
Tioop = Tioop + Topadjust + (Cload – Csl) * fl
where:
Topadjust is reported above in the Output Delay
Adjustment section.
Cload is the capacitive load for the design.
Table 2:
Constants for Use in Calculation of Tioop
Standard
Csl
(pF)
fl
(ns/pF)
LVTTL Fast Slew Rate, 2mA drive
35
0.41
LVTTL Fast Slew Rate, 4mA drive
35
0.20
LVTTL Fast Slew Rate, 6mA drive
35
0.13
LVTTL Fast Slew Rate, 8mA drive
35
0.079
LVTTL Fast Slew Rate, 12mA drive
35
0.044
LVTTL Fast Slew Rate, 16mA drive
35
0.043
LVTTL Fast Slew Rate, 24mA drive
35
0.033
LVTTL Slow Slew Rate, 2mA drive
35
0.41
LVTTL Slow Slew Rate, 4mA drive
35
0.20
LVTTL Slow Slew Rate, 6mA drive
35
0.10
LVTTL Slow Slew Rate, 8mA drive
35
0.086
LVTTL Slow Slew Rate, 12mA drive
35
0.058
LVTTL Slow Slew Rate, 16mA drive
35
0.050
LVTTL Slow Slew Rate, 24mA drive
35
0.048
LVCMOS2
35
0.041
LVCMOS18
35
0.050
PCI 33 MHZ 3.3 V
10
0.050
PCI 66 MHz 3.3 V
10
0.033
GTL
0
0.014
GTL+
0
0.017
HSTL Class I
20
0.022
HSTL Class III
20
0.016
HSTL Class IV
20
0.014
SSTL2 Class I
30
0.028
SSTL2 Class II
30
0.016
SSTL3 Class I
30
0.029
SSTL3 Class II
30
0.016
CTT
20
0.035
AGP
10
0.037
Notes:
1.
I/O parameter measurements are made with the capacitance
values shown above. See the Application Examples for
appropriate terminations.
2.
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
Table 3:
Delay Measurement Methodology
Standard
VL
1
VH
1
Meas.
Point
VREF
(Typ)2
LVTTL
03
1.4
-
LVCMOS2
02.5
1.125
-
PCI33_3
Per PCI Spec
-
PCI66_3
Per PCI Spec
-
GTL
VREF –0.2
VREF +0.2
VREF
0.80
GTL+
VREF –0.2
VREF +0.2
VREF
1.0
HSTL Class I
VREF –0.5
VREF +0.5
VREF
0.75
HSTL Class III
VREF –0.5
VREF +0.5
VREF
0.90
HSTL Class IV
VREF –0.5
VREF +0.5
VREF
0.90
SSTL3 I & II
VREF –1.0
VREF +1.0
VREF
1.5
SSTL2 I & II
VREF –0.75
VREF +0.75
VREF
1.25
CTT
VREF –0.2
VREF +0.2
VREF
1.5
AGP
VREF –
(0.2xVCCO)
VREF +
(0.2xVCCO)
VREF
Per
AGP
Spec
LVDS
1.2 – 0.125
1.2 + 0.125
1.2
LVPECL
1.6 – 0.3
1.6 + 0.3
1.6
Notes:
1.
Input waveform switches between VLand VH.
2.
Measurements are made at VREF (Typ), Maximum, and
Minimum. Worst-case values are reported.
I/O parameter measurements are made with the capacitance
values shown in
appropriate terminations.
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
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