參數(shù)資料
型號: XCV405E-6FG676I
廠商: XILINX INC
元件分類: FPGA
英文描述: Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
中文描述: FPGA, 2400 CLBS, 129600 GATES, 357 MHz, PBGA676
封裝: PLASTIC, FBGA-676
文件頁數(shù): 15/20頁
文件大?。?/td> 191K
代理商: XCV405E-6FG676I
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 3 of 4
DS025-3 (v2.3.2) March 14, 2003
4
1-800-255-7778
R
LVDS DC Specifications
LVPECL DC Specifications
These values are valid at the output of the source termination pack shown under LVPECL, with a 100
differential load only.
The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
ranges. The following table summarizes the DC output specifications of LVPECL.
DC Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply Voltage
VCCO
2.375
2.5
2.625
V
Output High Voltage for Q and Q
VOH
RT = 100 across Q and Q signals
1.25
1.425
1.6
V
Output Low Voltage for Q and Q
VOL
RT = 100 across Q and Q signals
0.9
1.075
1.25
V
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
VODIFF
RT = 100 across Q and Q signals
250
350
450
mV
Output Common-Mode Voltage
VOCM
RT = 100 across Q and Q signals
1.125
1.25
1.375
V
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
VIDIFF
Common-mode input voltage = 1.25 V
100
350
NA
mV
Input Common-Mode Voltage
VICM
Differential input voltage =
±350 mV
0.2
1.25
2.2
V
Notes:
1.
Refer to the Design Consideration section for termination schematics.
DC Parameter
Min
Max
Min
Max
Min
Max
Units
VCCO
3.0
3.3
3.6
V
VOH
1.8
2.11
1.92
2.28
2.13
2.41
V
VOL
0.96
1.27
1.06
1.43
1.30
1.57
V
VIH
1.49
2.72
1.49
2.72
1.49
2.72
V
VIL
0.86
2.125
0.86
2.125
0.86
2.125
V
Differential Input Voltage
0.3
-
0.3
-
0.3
-
V
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