參數(shù)資料
型號: XCV812E-8FG900C
廠商: Xilinx Inc
文件頁數(shù): 24/118頁
文件大小: 0K
描述: IC FPGA 1.8V C-TEMP 900-FBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標準包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 4704
邏輯元件/單元數(shù): 21168
RAM 位總計: 1146880
輸入/輸出數(shù): 556
門數(shù): 254016
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 900-BBGA
供應(yīng)商設(shè)備封裝: 900-FBGA
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
Module 2 of 4
9
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Figure 11 is a diagram of the Virtex-E Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE
1149.1 Test Access Port controller, and the Instruction Register with decodes.
Figure 11: Virtex-E Family Boundary Scan Logic
D
Q
D
Q
IOB
M
U
X
BYPASS
REGISTER
IOB
TDO
TDI
IOB
1
0
1
0
1
0
1
0
1
0
sd
LE
DQ
D
Q
D
Q
1
0
1
0
1
0
1
0
DQ
LE
sd
LE
DQ
sd
LE
DQ
IOB
D
Q
1
0
DQ
LE
sd
IOB.T
DATA IN
IOB.I
IOB.Q
IOB.T
IOB.I
SHIFT/
CAPTURE
CLOCK DATA
REGISTER
DATAOUT
UPDATE
EXTEST
X9016
INSTRUCTION REGISTER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV812E-8FG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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