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參數(shù)資料
| 型號： | XCV812E-8FG900C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 29/118頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 900-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標準包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 4704 |
| 邏輯元件/單元數(shù)： | 21168 |
| RAM 位總計： | 1146880 |
| 輸入/輸出數(shù)： | 556 |
| 門數(shù)： | 254016 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 900-BBGA |
| 供應商設備封裝： | 900-FBGA |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
14
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Master-Serial Mode
In master-serial mode, the CCLK output of the FPGA drives
a Xilinx Serial PROM that feeds bit-serial data to the DIN
input. The FPGA accepts this data on each rising CCLK
edge. After the FPGA has been loaded, the data for the next
device in a daisy-chain is presented on the DOUT pin after
the rising CCLK edge.
The interface is identical to slave-serial except that an inter-
nal oscillator is used to generate the configuration clock
(CCLK). A wide range of frequencies can be selected for
CCLK which always starts at a slow default frequency. Con-
figuration bits then switch CCLK to a higher frequency for
the remainder of the configuration. Switching to a lower fre-
quency is prohibited.
The CCLK frequency is set using the ConfigRate option in
the bitstream generation software. The maximum CCLK fre-
quency that can be selected is 60 MHz. When selecting a
CCLK frequency, ensure that the serial PROM and any
daisy-chained FPGAs are fast enough to support the clock
rate.
On power-up, the CCLK frequency is approximately
2.5 MHz. This frequency is used until the ConfigRate bits
have been loaded when the frequency changes to the
selected ConfigRate. Unless a different frequency is speci-
fied in the design, the default ConfigRate is 4 MHz.
Figure 13 shows a full master/slave system. In this system,
the left-most device operates in master-serial mode. The
remaining devices operate in slave-serial mode. The SPROM
RESET pin is driven by INIT, and the CE input is driven by
DONE. There is the potential for contention on the DONE pin,
depending on the start-up sequence options chosen.
Figure 13: Master/Slave Serial Mode Circuit Diagram
VIRTEX-E
MASTER
SERIAL
VIRTEX-E,
XC4000XL,
SLAVE
XC1701L
PROGRAM
M2
M0 M1
DOUT
CCLK
CLK
3.3V
DATA
CE
CEO
RESET/OE
DONE
DIN
INIT
DONE
PROGRAM
CCLK
DIN
DOUT
M2
M0 M1
(Low Reset Option Used)
330
Ω
XCVE_ds_013_050103
N/C
Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor
of 330
Ω should be added to the common DONE line. (For Spartan-XL devices, add a 4.7K Ω
pull-up resistor.) This pull-up is not needed if the DriveDONE attribute is set. If used,
DriveDONE should be selected only for the last device in the configuration chain.
Optional Pull-up
Resistor on Done
1
Figure 14: Slave-Serial Mode Programming Switching Characteristics
4 TCCH
3 TCCO
5 TCCL
2 TCCD
1 TDCC
DIN
CCLK
DOUT
(Output)
X5379_a
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-8FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCVR-040L31 | 制造商:WWP 功能描述: |
| XCW 10 | 制造商:G & J HALL 功能描述:COUNTERSINK HEXIBIT 10MM 制造商:G & J HALL 功能描述:COUNTERSINK, HEXIBIT, 10MM 制造商:G & J HALL 功能描述:COUNTERSINK, HEXIBIT, 10MM; Drill Bit Size Metric:10mm; Overall Length:30.5mm; SVHC:No SVHC (19-Dec-2012); Countersink Angle:90; Drill Bit Type:Countersink; Drill Point Diameter:10mm; External Diameter:10mm; Head Diameter:10mm; ;RoHS Compliant: NA |
| XCW10 | 制造商:G & J HALL 功能描述:COUNTERSINK HEXIBIT |
| XCW15 | 制造商:G & J HALL 功能描述:COUNTERSINK HEXIBIT |
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