參數(shù)資料
型號(hào): XCV812E-8FG900C
廠商: Xilinx Inc
文件頁(yè)數(shù): 45/118頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 1.8V C-TEMP 900-FBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 4704
邏輯元件/單元數(shù): 21168
RAM 位總計(jì): 1146880
輸入/輸出數(shù): 556
門數(shù): 254016
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 900-BBGA
供應(yīng)商設(shè)備封裝: 900-FBGA
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
28
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
At the third rising edge of CLKA, the TBCCS parameter is
violated with two writes to memory location 0x0F. The DOA
and DOB busses reflect the contents of the DIA and DIB
busses, but the stored value at 0x0F is invalid.
At the fourth rising edge of CLKA, a read operation is per-
formed at memory location 0x0F and invalid data is present
on the DOA bus. Port B also executes a read operation to
memory location 0x0F and also reads invalid data.
At the fifth rising edge of CLKA a read operation is per-
formed that does not violate the TBCCS parameter to the
previous write of 0x7E by Port B. THe DOA bus reflects the
recently written value by Port B.
Figure 33: Timing Diagram for Single Port Block SelectRAM+ Memory
ds022_0343_121399
CLK
TBPWH
TBACK
ADDR
00
DDDD
MEM (00)
CCCC
MEM (7E)
0F
CCCC
7E
8F
BBBB
2222
DIN
DOUT
EN
RST
WE
DISABLED
READ
WRITE
READ
DISABLED
TBDCK
TBECK
TBWCK
TBCKO
TBPWL
Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory
ds022_035_121399
CLK_A
PORT
A
PORT
B
ADDR_A
00
7E
0F
00
7E
1A
0F
7E
AAAA
9999
AAAA
0000
1111
2222
AAAA
9999
AAAA
UNKNOWN
EN_A
WE_A
DI_A
DO_A
1111
2222
FFFF
BBBB
1111
AAAA
MEM (00)
9999
2222
FFFF
BBBB
UNKNOWN
CLK_B
ADDR_B
EN_B
WE_B
DI_B
DO_B
TBCCS
VIOLATION
TBCCS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV812E-8FG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCVR-040L31 制造商:WWP 功能描述:
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