參數(shù)資料
型號： XE8801AMI000WP
廠商： Semtech
文件頁數(shù)： 128/135頁
文件大?。?/td> 0K
描述： SENSING MACHINE WITH 16 + 10 BIT
標準包裝： 558
系列： XE880x
應用： 感測機
核心處理器： Coolrisc816?
程序存儲器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 模具
包裝： 托盤
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
其它名稱： Q2722595
Semtech 2005
www.semtech.com
16-7
XE8801A – SX8801R
PGA1_GAIN
: (rw) sets the gain of the first stage: 0
1, 1
10.
PGA2_GAIN
: (rw) sets the gain of the second stage: 00
1, 01
2, 10
5, 11
10.
PGA3_GAIN
: (rw) sets the gain of the third stage to PGA3_GAIN[6:0]
1/12.
PGA2_OFFSET
: (rw) sets the offset of the second stage between –1 and +1, with increments of 0.2. The MSB gives the sign
(0
→ positive, 1 → negative); amplitude is coded with the bits PGA2_OFFSET[5:0].
PGA3_OFFSET
: (rw) sets the offset of the third stage between –5.25 and +5.25, with increments of 1/12. The MSB gives the
sign (0
→ positive, 1 → negative); amplitude is coded with the bits PGA3_OFFSET[5:0].
BUSY
: (r) set to 1 if a conversion is running. Note that the flag is set at the effective start of the conversion. Since the ADC is
generally synchronized on a lower frequency clock than the CPU, there might be a small delay (max. 1 cycle of the ADC
sampling frequency) between the writing of the START or CONT bits and the appearance of BUSY flag.
DEF
: (w) sets all values to their defaults (PGA disabled, max speed, nominal modulator bias current, 2 elementary
conversions, over-sampling rate of 32) and starts a new conversion without waiting the end of the preceding one.
AMUX(4:0):
(rw) AMUX[4] sets the mode (0
4 differential inputs, 1
7 inputs with A(0) = common reference) AMUX(3)
sets the sign (0
straight, 1
cross) AMUX[2:0] sets the channel.
VMUX
: (rw) sets the differential reference channel (0
R(1)
and R(0), 1
R(3)
and R(2)).
(r = read; w = write; rw = read & write)
16.4.3
Continuous-Time vs. On-Request
The ADC can be operated in two distinct modes: "continuous-time" and "on-request" modes (selected using the bit
CONT
).
In "continuous-time" mode, the input signal is repeatedly converted into digital. After a conversion is finished, a new
one is automatically initiated. The new value is then written in the result register, and the corresponding internal
trigger pulse is generated. This operation is sketched in Figure 16-3. The conversion time in this case is defined as
TCONV.
Internal Trig
Ouput Code
RegACOut[15:0]
T
CONV
BUSY
IRQ
Figure 16-3. ADC "continuous-time" operation
Figure 16-4. ADC "on-request" operation
In the "on-request" mode, the internal behaviour of the converter is the same as in the "continuous-time" mode, but
the conversion is initiated on user request (with the START bit). As shown in Figure 16-4, the conversion time is also
TCONV. Note that the flag is set at the effective start of the conversion. Since the ADC is generally synchronized on a
lower frequency clock than the CPU, there might be a small delay (max. 1 cycle of the ADC sampling frequency)
between the writing of the START or CONT bits and the appearance of BUSY flag.
Internal Trig
Ouput Code
RegACOut[15:0]
T
CONV
Request
START
BUSY
IRQ
Not
Recommended
for
New
Designs
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