參數(shù)資料
型號： XE8801AMI000WP
廠商： Semtech
文件頁數(shù)： 87/135頁
文件大小： 0K
描述： SENSING MACHINE WITH 16 + 10 BIT
標(biāo)準(zhǔn)包裝： 558
系列： XE880x
應(yīng)用： 感測機(jī)
核心處理器： Coolrisc816?
程序存儲器類型： 閃存（22 kB）
控制器系列： XE8000
RAM 容量： 512 x 8
接口： UART，USRT
輸入/輸出數(shù)： 24
電源電壓： 2.4 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 模具
包裝： 托盤
配用： XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
其它名稱： Q2722595
Semtech 2005
www.semtech.com
9-2
XE8801A – SX8801R
9.1
Features
The XE8801AM and SX8801R chips support 8 event sources, divided into 2 levels of priority.
9.2
Overview
A CPU event is generated and memorized when an event source becomes active. The 8 event sources are divided
into 2 levels of priority: High (4 event sources) and Low (4 event sources). Those 2 levels of priority are directly
mapped to those supported by the CoolRisc (EV0 and EV1; see CoolRisc documentation for more information).
RegEvn is an 8-bit register containing flags for the event sources. Those flags are set when the event is enabled
(i.e. if the corresponding bit in the registers RegEvnEn is set) and a rising edge is detected on the corresponding
event source.
Once memorized, writing a ‘1’ in the corresponding bit of RegEvn clears an event flag. Writing a ‘0’ does not
modify the flag. All interrupts are automatically cleared after a reset.
Two registers are provided to facilitate the writing of event service software. RegEvnPriority contains the number
of the highest priority event set (its value is 0xFF when no event is set). RegEvnEvn indicates the priority level of
the current interrupts. RegEvnEvn and RegEvnPriority ‘s values are dependent upon the memorized state of the
events (as reflected in flags in RegEvn).
9.3
Register map
pos.
RegEvn
rw
reset
function
7
RegEvn[7]
r
c1
0 resetsystem
event #7 (high priority)
clear event #7 when written 1
6
RegEvn[6]
r
c1
0 resetsystem
event #6 (high priority)
clear event #6 when written 1
5
RegEvn[5]
r
c1
0 resetsystem
event #5 (high priority)
clear event #5 when written 1
4
RegEvn[4]
r
c1
0 resetsystem
event #4 (high priority)
clear event #4 when written 1
3
RegEvn[3]
r
c1
0 resetsystem
event #3 (low priority)
clear event #3 when written 1
2
RegEvn[2]
r
c1
0 resetsystem
event #2 (low priority)
clear event #2 when written 1
1
RegEvn[1]
r
c1
0 resetsystem
event #1 (low priority)
clear event #1 when written 1
0
RegEvn[0]
r
c1
0 resetsystem
event #0 (low priority)
clear event #0 when written 1
Table 9-1: RegEvn
Not
Recommended
for
New
Designs
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