Unless otherwise specified: Temperature T
參數(shù)資料
型號: XE8801AMI000WP
廠商: Semtech
文件頁數(shù): 6/135頁
文件大?。?/td> 0K
描述: SENSING MACHINE WITH 16 + 10 BIT
標(biāo)準(zhǔn)包裝: 558
系列: XE880x
應(yīng)用: 感測機(jī)
核心處理器: Coolrisc816?
程序存儲器類型: 閃存(22 kB)
控制器系列: XE8000
RAM 容量: 512 x 8
接口: UART,USRT
輸入/輸出數(shù): 24
電源電壓: 2.4 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 模具
包裝: 托盤
配用: XE8000MP-ND - PROG BOARD AND PROSTART2 CARD
其它名稱: Q2722595
Semtech 2005
www.semtech.com
16-18
XE8801A – SX8801R
16.8.2
Specifications
Unless otherwise specified: Temperature TA = +25°C, VDD = +5V, GND = 0V, VREF = +5V, VIN = 0V, RC frequency fRC = 2MHz, sampling frequency
fS = 500kHz, Overall PGA gain GDTOT = 1, offsets GDOff2 = GDOff3 = 0. Power operation: normal (IB_AMP_ADC[1:0] = IB_AMP_PGA[1:0] =
'11'). For resolution n = 12 bits: OSR = 32 and NELCONV = 4. For resolution n = 16 bits: OSR = 512 and NELCONV = 2.
VALUE
PARAMETER
MIN
TYP
MAX
UNITS
COMMENTS/CONDITIONS
ANALOG
INPUT
CHARACTERISTICS
Differential Input Voltage Ranges
VIN = (VINP - VINN)
Reference Voltage Range
VREF = (VREFP – VREFN)
-2.42
-24.2
-2.42
+2.42
+24.2
+2.42
VDD
V
mV
V
Gain = 1, OSR = 32 (Note 1)
Gain = 100, OSR = 32
Gain = 1000, OSR = 32
PROGRAMMABLE
GAIN
AMPLIFIERS (PGA)
Total PGA Gain, GDTOT
PGA1 Gain, GD1
PGA2 Gain, GD2
PGA3 Gain, GD3
Gain Setting Precision (each stage)
Gain Temperature Dependence
Offset
PGA2 Offset, GDoff2
PGA3 Offset, GDoff3
Offset Setting Precision (PGA2 or 3)
Offset Temperature Dependence
Input Impedance
PGA1
PGA2, PGA3
Output RMS Noise
PGA1
PGA2
PGA3
0.5
1
0
-3
-1
-127/12
-3
1500
150
±0.5
±5
±0.5
±5
205
340
365
1000
10
127/12
+3
+1
+127/12
+3
V/V
%
ppm/°C
V/V
%
ppm/°C
k
k
k
V
See Table 16-14
See Table 16-15
Step=1/12 V/V, See Table 16-17
Step=0.2 V/V, See Table 16-16
Step=1/12 V/V, See Table 16-18
(Note 2)
PGA1 Gain = 1 (Note 3)
PGA1 Gain = 10 (Note 3)
Maximal gain (Note 3)
(Note 4)
(Note 5)
(Note 6)
ADC STATIC PERFORMANCE
Resolution, n
No Missing Codes
Gain Error
Offset Error
Integral Non-Linearity, INL
Resolution n = 16 Bits
Differential Non-Linearity, DNL
Resolution n = 16 Bits
Power Supply Rejection Ratio, PSRR
6
±0.15
±1
±1.0
±0.5
78
72
16
Bits
% of FS
LSB
dB
(Note 7)
(Note 8)
(Note 9)
n = 16 bits (Note 10)
(Note 11)
(Note 12)
VDD = 5V ± 0.3V (Note 13)
VDD = 3V ± 0.3V (Note 13)
DYNAMIC PERFORMANCE
Sampling Frequency, fS
Conversion Time, TCONV
Throughput Rate (Continuous Mode),
1/TCONV
Nbr of Initialization Cycles, NINIT
Nbr of End Conversion Cycles, NEND
PGA Stabilization Delay
3
0
133
1027
3.76
0.49
OSR
2
5
kHz
cycles/fS
kSps
cycles
n = 12 bits (Note 14)
n = 16 bits (Note 14)
n = 12 bits, fS = 500kHz
n = 16 bits, fS = 500kHz
(Note 15)
DIGITAL OUTPUT
ADC Output Data Coding
Binary Two’s Complement
See Table 16-24 and Table
16-25
Not
Recommended
for
New
Designs
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