- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376453 > XR16C2852 (Exar Corporation) 3.3V AND 5V DUART WITH 128-BYTE FIFO PDF資料下載
參數(shù)資料
| 型號： | XR16C2852 |
| 廠商： | Exar Corporation |
| 英文描述： | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| 中文描述： | 3.3V和5V杜阿爾特128字節(jié)FIFO |
| 文件頁數(shù)： | 42/42頁 |
| 文件大?。?/td> | 574K |
| 代理商： | XR16C2852 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當(dāng)前第42頁
á
XR16C2852
3.3V AND 5V DUART WITH 128-BYTE FIFO
REV. 2.0.0
II
4.1 R
ECEIVE
H
OLDING
R
EGISTER
(RHR) - R
EAD
- O
NLY
........................................................................... 20
4.2 T
RANSMIT
H
OLDING
R
EGISTER
(THR) - W
RITE
-O
NLY
......................................................................... 20
4.3 B
AUD
R
ATE
G
ENERATOR
D
IVISORS
(DLL
AND
DLM) - R
EAD
/W
RITE
................................................... 20
4.4 I
NTERRUPT
E
NABLE
R
EGISTER
(IER) - R
EAD
/W
RITE
.......................................................................... 20
4.4.1 IER versus Receive FIFO Interrupt Mode Operation ............................................................................... 20
4.4.2 IER versus Receive/Transmit FIFO Polled Mode Operation.................................................................... 21
4.5 I
NTERRUPT
S
TATUS
R
EGISTER
(ISR) - R
EAD
-O
NLY
............................................................................ 21
4.5.1 Interrupt Generation:................................................................................................................................ 22
4.5.2 Interrupt Clearing: .................................................................................................................................... 22
T
ABLE
9: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
............................................................................................................................... 22
4.6 FIFO C
ONTROL
R
EGISTER
(FCR) - W
RITE
-O
NLY
............................................................................... 22
T
ABLE
10: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
................................................................................................... 24
4.7 L
INE
C
ONTROL
R
EGISTER
(LCR) - R
EAD
/W
RITE
................................................................................ 24
4.8 A
LTERNATE
F
UNCTION
R
EGISTER
(AFR) - R
EAD
/W
RITE
..................................................................... 25
T
ABLE
11: P
ARITY
SELECTION
................................................................................................................................................................ 25
4.9 M
ODEM
C
ONTROL
R
EGISTER
(MCR)
OR
G
ENERAL
P
URPOSE
O
UTPUTS
C
ONTROL
- R
EAD
/W
RITE
....... 25
4.10 L
INE
S
TATUS
R
EGISTER
(LSR) - R
EAD
O
NLY
................................................................................... 26
4.11 M
ODEM
S
TATUS
R
EGISTER
(MSR) - R
EAD
O
NLY
............................................................................. 27
4.12 S
CRATCH
P
AD
R
EGISTER
(SPR) - R
EAD
/W
RITE
............................................................................... 27
4.13 E
NHANCED
M
ODE
S
ELECT
R
EGISTER
(EMSR) ................................................................................. 27
T
ABLE
12: S
CRATCHPAD
S
WAP
S
ELECTION
............................................................................................................................................ 27
4.14 FIFO L
EVEL
R
EGISTER
(FLVL) - R
EAD
-O
NLY
.................................................................................. 28
T
ABLE
13: A
UTO
RTS H
YSTERESIS
....................................................................................................................................................... 28
4.15 B
AUD
R
ATE
G
ENERATOR
R
EGISTERS
(DLL
AND
DLM) - R
EAD
/W
RITE
.............................................. 28
4.16 D
EVICE
I
DENTIFICATION
R
EGISTER
(DVID) - R
EAD
O
NLY
................................................................. 28
4.17 D
EVICE
R
EVISION
R
EGISTER
(DREV) - R
EAD
O
NLY
......................................................................... 28
4.18 T
RIGGER
L
EVEL
/ FIFO D
ATA
C
OUNT
R
EGISTER
(TRG) - W
RITE
-O
NLY
............................................ 28
4.19 FIFO D
ATA
C
OUNT
R
EGISTER
(FC) - R
EAD
-O
NLY
........................................................................... 28
4.20 F
EATURE
C
ONTROL
R
EGISTER
(FCTR) - R
EAD
/W
RITE
.................................................................... 28
T
ABLE
14: T
RIGGER
T
ABLE
S
ELECT
....................................................................................................................................................... 29
4.21 E
NHANCED
F
EATURE
R
EGISTER
(EFR) ............................................................................................ 29
T
ABLE
15: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
............................................................................................................................... 30
4.22 S
OFTWARE
F
LOW
C
ONTROL
R
EGISTERS
(XOFF1, XOFF2, XON1, XON2) - R
EAD
/W
RITE
............... 31
T
ABLE
16: UART RESET CONDITIONS FOR CHANNEL A AND B................................................................................................... 31
ABSOLUTE MAXIMUM RATINGS ..................................................................................32
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)32
ELECTRICAL CHARACTERISTICS................................................................................32
DC E
LECTRICAL
C
HARACTERISTICS
...........................................................................................................32
AC E
LECTRICAL
C
HARACTERISTICS
...........................................................................................................33
F
IGURE
14. C
LOCK
T
IMING
.................................................................................................................................................................... 34
F
IGURE
15. M
ODEM
I
NPUT
/O
UTPUT
T
IMING
F
OR
C
HANNELS
A & B......................................................................................................... 34
F
IGURE
16. D
ATA
B
US
R
EAD
T
IMING
..................................................................................................................................................... 35
F
IGURE
17. D
ATA
B
US
W
RITE
T
IMING
.................................................................................................................................................... 35
F
IGURE
18. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A & B................................................................. 36
F
IGURE
19. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A & B............................................................... 36
F
IGURE
20. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA D
ISABLED
]
FOR
C
HANNELS
A & B............................................... 37
F
IGURE
21. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA E
NABLED
]
FOR
C
HANNELS
A & B................................................ 37
F
IGURE
22. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
D
ISABLED
]
FOR
C
HANNELS
A & B................................... 38
F
IGURE
23. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
E
NABLED
]
FOR
C
HANNELS
A & B.................................... 38
PACKAGE DIMENSIONS (44 PIN PLCC).......................................................................39
R
EVISION
H
ISTORY
...................................................................................................................................40
TABLE OF CONTENTS ................................................................................................................................. I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16C2852CJ | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2852IJ | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C850CJ | UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
| XR16C850CM | UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
| XR16C850CP | UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C2852_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
| XR16C2852CJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16C2852CJ-0A-EB | 功能描述:UART 接口集成電路 Supports C2852 44 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2852CJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2852CJTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。