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參數(shù)資料
| 型號： | XR16C850CM-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 55/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 128B 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 1，UART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1658 XR16C850CM-F-ND |
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XR16C850
xr
2.97V TO 5.5V UART WITH 128-BYTE FIFO
REV. 2.3.1
8
1.0 PRODUCT DESCRIPTION
The XR16C850 (850) provides serial asynchronous receive data synchronization, parallel-to-serial and serial-
to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for
converting the serial data stream into parallel data that is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip.
The XR16C850 represents such an integration with greatly enhanced features. The 850 is fabricated using an
advanced CMOS process.
Enhanced Features
The 850 is an upward solution that provides 128 bytes of transmit and receive FIFO memory, instead of 32
bytes provided in the 16C650A, 16 bytes in the 16C550, or none in the 16C450. The 850 is designed to work
with high speed modems and shared network environments, that require fast data processing time. Increased
performance is realized in the 850 by the larger transmit and receive FIFOs. This allows the external processor
to handle more networking tasks within a given time. For example, the ST16C550 with a 16 byte FIFO, unloads
16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at
115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However
with the 128 byte FIFO in the 850, the data buffer will not require unloading/loading for 12.2 ms. This increases
the service interval giving the external CPU additional time for other applications and reducing the overall
UART interrupt servicing time. In addition, the programmable FIFO trigger level interrupt and automatic
hardware/software flow control is uniquely provided for maximum data throughput performance. The
combination of the above greatly reduces the bandwidth requirement of the external controlling CPU,
increases performance, and reduces power consumption.
The 850 provides a RS-485 half-duplex direction control signal, pin OP1#/RS485 to select the external
transceiver direction. It automatically changes the state of the output pin for receive state after the last stop-bit
of the last character has been shifted out of the TX shift register. Afterward, upon loading a TX data byte, it
changes state of the output pin back for transmit state. The RS-485 direction control pin is not activated after
reset. To activate the direction control function, the user has to set EFR Bit-4, and FCTR Bit-3 to “1”. This pin
(OP1#/RS485) is high for receive state, low for transmit state.
Data Bus Interface
Two data bus interfaces are available to the user. The PC mode allows direct interconnect to the PC ISA bus
while the Intel Bus Mode operates similar to the standard CPU interface available on the 16C450/550/650A.
When the PC mode is selected, the external logic circuitry required for PC COM port address decode and chip
select is eliminated. These functions are provided internally in the 850.
Data Rate
The 850 is capable of operation up to 1.5 Mbps with a 24 MHz crystal or external clock input with a 16X
sampling clock. However, it is possible to operate up to 2.25 Mbps with a 36 MHz external clock for devices
with top mark date code of "F2 YYWW" and newer, and up to 2 Mbps with a 33 MHz external clock for devices
with top mark date code of "EC YYWW" and older. With a crystal of 14.7456 MHz and through a software
option, the user can select data rates up to 921.6 Kbps.
The rich feature set of the 850 is available through internal registers. Automatic hardware/software flow control,
selectable transmit and receive FIFO trigger levels, selectable TX and RX baud rates, infrared encoder/
decoder interface, modem interface controls, and a sleep mode are all standard features. In addition, there is a
PC Mode that has two additional three state interrupt lines and one selectable open source interrupt output.
The open source interrupt scheme allows multiple interrupts to be combined in a “WIRE-OR” operation, thus
reducing the number of interrupt lines in larger systems. Following a power on reset or an external reset, the
850 is software compatible with previous generation of UARTs, 16C450 and 16C550 and 16C650A.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XR16C850CMTR-F | 功能描述:UART 接口集成電路 UART w/128 Bytes FIFO & IrDA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C850CP | 制造商:EXAR 制造商全稱:EXAR 功能描述:UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
| XR16C850CQ | 制造商:EXAR 制造商全稱:EXAR 功能描述:UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
| XR16C850IJ | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART WITH 128-BYTE FIFO |
| XR16C850IJ-F | 功能描述:UART 接口集成電路 UARTW/128BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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