REV. 2.3.1 2.97V TO 5.5V UART WITH 128-BYTE FIFO 17 NOTE: Table-B" />
參數(shù)資料
型號: XR16C850CM-F
廠商: Exar Corporation
文件頁數(shù): 9/56頁
文件大?。?/td> 0K
描述: IC UART FIFO 128B 48TQFP
標準包裝: 250
特點: *
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
其它名稱: 1016-1658
XR16C850CM-F-ND
xr
XR16C850
REV. 2.3.1
2.97V TO 5.5V UART WITH 128-BYTE FIFO
17
NOTE: Table-B selected as Trigger Table for
FIGURE 11. RECEIVER OPERATION IN NON-FIFO MODE
FIGURE 12. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
Receive Data Shift
Register (RSR)
RXFIFO1
16X Clock
Error
Ta
gs
(128-set
s)
E
rror
Tags
in
LSR
bi
ts
4:2
128 bytes by 11-bit
wide
FIFO
Receive Data Characters
FIFO
Trigger=16
Example
:
- RX FIFO trigger level selected at 16
bytes
(See Note Below)
Data fills to
24
Data falls to
8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
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