REV. 2.3.1 14 2.11 Programmable Baud Rate Generator The UART has its own Baud R" />
參數(shù)資料
型號: XR16C850CM-F
廠商: Exar Corporation
文件頁數(shù): 6/56頁
文件大?。?/td> 0K
描述: IC UART FIFO 128B 48TQFP
標(biāo)準(zhǔn)包裝: 250
特點: *
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
其它名稱: 1016-1658
XR16C850CM-F-ND
XR16C850
xr
2.97V TO 5.5V UART WITH 128-BYTE FIFO
REV. 2.3.1
14
2.11
Programmable Baud Rate Generator
The UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter. The prescaler is
controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input
crystal or external clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides
this clock by a programmable divisor between 1 and (216 -1) to obtain a 16X sampling clock of the serial data
rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG
divisor (DLL and DLM registers) defaults to a random value upon power up or a reset. Therefore, the BRG
must be programmed during initialization to the operating data rate.
Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the
operating data rate. Table 4 shows the standard data rates available with a 14.7456 MHz crystal or external
clock at 16X clock rate. When using a non-standard data rate crystal or external clock, the divisor value can be
calculated for DLL/DLM with the following equation.
FIGURE 8. BAUD RATE GENERATOR
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
TABLE 4: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=1
OUTPUT Data Rate
MCR Bit-7=0
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM
PROGRAM
VALUE (HEX)
DLL
PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
115.2k
460.8k
2
02
00
02
0
230.4k
921.6k
1
01
00
01
0
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X
Sampling
Rate Clock to
Transmitter
and Receiver
Baud Rate
Generator
Logic
CLKSEL = VCC
CLKSEL = GND
During
Initialization or
Reset
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