REV. 1.2.1 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 19 2.22 Internal Loopback The 2752 UART provides an internal loopback capability " />
參數(shù)資料
型號(hào): XR16L2752IJ-F
廠商: Exar Corporation
文件頁數(shù): 11/49頁
文件大小: 0K
描述: IC UART FIFO 64B DUAL 44PLCC
標(biāo)準(zhǔn)包裝: 27
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.25 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱: 1016-1650
XR16L2752IJ-F-ND
xr
XR16L2752
REV. 1.2.1
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
19
2.22
Internal Loopback
The 2752 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,
DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else
upon exiting the loopback test the UART may detect and report a false “break” signal. Also, Auto RTS/CTS
hardware flow control is not supported during internal loopback.
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
Modem
/
G
eneral
P
u
rpose
Control
Logic
Inte
rn
al
Data
B
u
sLines
a
n
d
Contr
o
lSignals
RTSA#/RTSB#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB#
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
(OP2A#/OP2B#)
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